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Diffstat (limited to 'src/southbridge/via/vt8231')
-rw-r--r--src/southbridge/via/vt8231/early_smbus.c2
-rw-r--r--src/southbridge/via/vt8231/ide.c6
-rw-r--r--src/southbridge/via/vt8231/lpc.c2
3 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/via/vt8231/early_smbus.c b/src/southbridge/via/vt8231/early_smbus.c
index 7bf1267b75..adbd186c87 100644
--- a/src/southbridge/via/vt8231/early_smbus.c
+++ b/src/southbridge/via/vt8231/early_smbus.c
@@ -129,7 +129,7 @@ static void smbus_print_error(unsigned char host_status_register)
print_err_hex8(host_status_register);
print_err("\n");
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ print_err("Interrupt/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
print_err("Bus Error\n");
diff --git a/src/southbridge/via/vt8231/ide.c b/src/southbridge/via/vt8231/ide.c
index 46479c4af3..3b402477d5 100644
--- a/src/southbridge/via/vt8231/ide.c
+++ b/src/southbridge/via/vt8231/ide.c
@@ -11,7 +11,7 @@ static void ide_init(struct device *dev)
unsigned char enables;
if (!conf->enable_native_ide) {
- // Run the IDE controller in 'compatiblity mode - i.e. don't use PCI
+ // Run the IDE controller in 'compatibility mode - i.e. don't use PCI
// interrupts. Using PCI ints confuses linux for some reason.
/* Setting reg 0x42 here does not work. It is set in mainboard/romstage.c
* It probably can only be changed while the IDE is disabled
@@ -22,7 +22,7 @@ static void ide_init(struct device *dev)
printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n", __func__);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
- enables &= ~0xc0; // compatability mode
+ enables &= ~0xc0; // compatibility mode
pci_write_config8(dev, 0x42, enables);
enables = pci_read_config8(dev, 0x42);
printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n", enables);
@@ -85,7 +85,7 @@ static void ide_init(struct device *dev)
printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
if (!conf->enable_native_ide) {
- // Use compatability mode - per award bios
+ // Use compatibility mode - per award bios
pci_write_config32(dev, 0x10, 0x0);
pci_write_config32(dev, 0x14, 0x0);
pci_write_config32(dev, 0x18, 0x0);
diff --git a/src/southbridge/via/vt8231/lpc.c b/src/southbridge/via/vt8231/lpc.c
index c6b74fdaa1..466b6df392 100644
--- a/src/southbridge/via/vt8231/lpc.c
+++ b/src/southbridge/via/vt8231/lpc.c
@@ -23,7 +23,7 @@ static void pci_routing_fixup(struct device *dev)
printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
if (dev) {
- /* initialize PCI interupts - these assignments depend
+ /* initialize PCI interrupts - these assignments depend
on the PCB routing of PINTA-D
PINTA = IRQ11