diff options
Diffstat (limited to 'src/southbridge/nvidia/ck804/bootblock.c')
| -rw-r--r-- | src/southbridge/nvidia/ck804/bootblock.c | 24 |
1 files changed, 22 insertions, 2 deletions
diff --git a/src/southbridge/nvidia/ck804/bootblock.c b/src/southbridge/nvidia/ck804/bootblock.c index 6d4b6a4777..29c10c8d0e 100644 --- a/src/southbridge/nvidia/ck804/bootblock.c +++ b/src/southbridge/nvidia/ck804/bootblock.c @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2010 Jonathan Kollasch <jakllsch@kollasch.net> + * Copyright (C) 2004 Tyan Computer + * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,7 +21,26 @@ #include <arch/io.h> #include <arch/romcc_io.h> -#include "southbridge/nvidia/ck804/enable_rom.c" +#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else +#define CK804_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif + +static void ck804_enable_rom(void) +{ + unsigned char byte; + device_t addr; + + /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ + /* Locate the ck804 LPC. */ + addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); + + /* Set the 4MB enable bit. */ + byte = pci_read_config8(addr, 0x88); + byte |= 0x80; + pci_write_config8(addr, 0x88, byte); +} static void bootblock_southbridge_init(void) { |