diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/early_pch.c | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/pch.h | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/ibexpeak/setup_heci_uma.c | 1 |
3 files changed, 7 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 2fa4b52d23..9edbcf6aa7 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -2,6 +2,7 @@ #include <arch/io.h> #include <console/console.h> +#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/smbus_host.h> #include <northbridge/intel/ironlake/ironlake.h> @@ -46,6 +47,10 @@ void ibexpeak_setup_bars(void) /* halt timer */ outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06); printk(BIOS_DEBUG, " done.\n"); + + pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR); + pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } void early_pch_init(void) diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 6565cd11f0..83e86c266c 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -22,6 +22,7 @@ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 +#define DEFAULT_HECIBAR ((u8 *)0xfed17000) #include <southbridge/intel/common/rcba.h> diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c index 70219e1adb..3f8b6617c4 100644 --- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c +++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c @@ -6,6 +6,7 @@ #include <device/pci_ops.h> #include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/ibexpeak/me.h> +#include <southbridge/intel/ibexpeak/pch.h> #include <types.h> #define HECIDEV PCI_DEV(0, 0x16, 0) |