diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/azalia.c | 19 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_smbus.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 23 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/pcie.c | 15 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/sata.c | 20 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/smbus.c | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/smihandler.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/usb.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/usb_ehci.c | 3 |
10 files changed, 38 insertions, 70 deletions
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index a701c47a81..4a2b50e4d4 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -30,9 +30,7 @@ static int set_bits(void *port, u32 mask, u32 val) reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -100,9 +98,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) static int wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { @@ -116,9 +112,8 @@ static int wait_for_ready(u8 *base) } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) @@ -130,14 +125,12 @@ static int wait_for_valid(u8 *base) reg32 |= (1 << 0) | (1 << 1); write32(base + 0x68, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index ea639f9fc4..3a1369a34b 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -21,8 +21,7 @@ int smbus_enable_iobar(uintptr_t base) return -1; /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - base | PCI_BASE_ADDRESS_SPACE_IO); + pci_write_config32(dev, SMB_BASE, base | PCI_BASE_ADDRESS_SPACE_IO); /* Set SMBus enable. */ pci_write_config8(dev, HOSTC, HST_EN); @@ -48,8 +47,7 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); } -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) +int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) { return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); } diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 5df36ddc81..1a5366fe87 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -61,8 +61,7 @@ void i82801gx_enable(struct device *dev) /* Ensure memory, io, and bus master are all disabled */ reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); pci_write_config32(dev, PCI_COMMAND, reg32); /* Hide this device if possible */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 8949e8d7e7..c24460cd81 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -52,8 +52,7 @@ static void i82801gx_enable_ioapic(struct device *dev) static void i82801gx_enable_serial_irqs(struct device *dev) { /* Set packet length and toggle silent mode bit for one frame. */ - pci_write_config8(dev, SERIRQ_CNTL, - (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); + pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); } /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control @@ -129,9 +128,7 @@ static void i82801gx_gpi_routing(struct device *dev) config_t *config = dev->chip_info; u32 reg32 = 0; - /* An array would be much nicer here, or some - * other method of doing this. - */ + /* An array would be much nicer here, or some other method of doing this. */ reg32 |= (config->gpi0_routing & 0x03) << 0; reg32 |= (config->gpi1_routing & 0x03) << 2; reg32 |= (config->gpi2_routing & 0x03) << 4; @@ -411,8 +408,7 @@ unsigned long acpi_fill_madt(unsigned long current) current = acpi_create_madt_lapics(current); /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); /* LAPIC_NMI */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *) @@ -675,14 +671,13 @@ static struct device_operations device_ops = { .final = lpc_final, }; -/* 27b0: 82801GH (ICH7 DH) */ -/* 27b8: 82801GB/GR (ICH7/ICH7R) */ -/* 27b9: 82801GBM/GU (ICH7-M/ICH7-U) */ -/* 27bc: 82NM10 (NM10) */ -/* 27bd: 82801GHM (ICH7-M DH) */ - static const unsigned short pci_device_ids[] = { - 0x27b0, 0x27b8, 0x27b9, 0x27bc, 0x27bd, 0 + 0x27b0, /* 82801GH (ICH7 DH) */ + 0x27b8, /* 82801GB/GR (ICH7/ICH7R) */ + 0x27b9, /* 82801GBM/GU (ICH7-M/ICH7-U) */ + 0x27bc, /* 82NM10 (NM10) */ + 0x27bd, /* 82801GHM (ICH7-M DH) */ + 0 }; static const struct pci_driver ich7_lpc __pci_driver = { diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 7efaca9130..4398ad56b0 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -129,8 +129,7 @@ static void root_port_init_config(struct device *dev) rp = root_port_number(dev); if (rp > rpc.num_ports) { - printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", - rp, rpc.num_ports); + printk(BIOS_ERR, "Found Root Port %d, expecting %d\n", rp, rpc.num_ports); return; } @@ -170,8 +169,7 @@ static void root_port_commit_config(struct device *dev) int coalesce = 0; if (dev->chip_info != NULL) { - struct southbridge_intel_i82801gx_config *config - = dev->chip_info; + struct southbridge_intel_i82801gx_config *config = dev->chip_info; coalesce = config->pcie_port_coalesce; } @@ -184,16 +182,14 @@ static void root_port_commit_config(struct device *dev) pcie_dev = rpc.ports[i]; if (pcie_dev == NULL) { - printk(BIOS_ERR, "Root Port %d device is NULL?\n", - i + 1); + printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1); continue; } if (pcie_dev->enabled) continue; - printk(BIOS_DEBUG, "%s: Disabling device\n", - dev_path(pcie_dev)); + printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(pcie_dev)); /* Disable this device if possible */ i82801gx_enable(pcie_dev); @@ -222,8 +218,7 @@ static void root_port_commit_config(struct device *dev) } } - printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", - rpc.orig_rpfn, rpc.new_rpfn); + printk(BIOS_SPEW, "ICH: RPFN 0x%08x -> 0x%08x\n", rpc.orig_rpfn, rpc.new_rpfn); RCBA32(RPFN) = rpc.new_rpfn; } diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c index 533cfef9a4..4b4511c4d8 100644 --- a/src/southbridge/intel/i82801gx/sata.c +++ b/src/southbridge/intel/i82801gx/sata.c @@ -28,8 +28,7 @@ static u8 get_ich7_sata_ports(void) case 0x27bc: return 0x3; default: - printk(BIOS_ERR, - "i82801gx_sata: error: cannot determine port config\n"); + printk(BIOS_ERR, "i82801gx_sata: error: cannot determine port config\n"); return 0; } } @@ -54,11 +53,9 @@ void sata_enable(struct device *dev) & AHCI_UNSUPPORTED); if (!ahci_supported) { - /* Fallback to IDE PLAIN for sata for the rest of the - initialization */ + /* Fallback to IDE PLAIN for sata for the rest of the initialization */ config->sata_mode = SATA_MODE_IDE_PLAIN; - printk(BIOS_DEBUG, - "AHCI not supported, falling back to plain mode.\n"); + printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n"); } } @@ -66,12 +63,10 @@ void sata_enable(struct device *dev) if (config->sata_mode == SATA_MODE_AHCI) { /* Set map to ahci */ pci_write_config8(dev, SATA_MAP, - (pci_read_config8(dev, SATA_MAP) - & ~0xc3) | 0x40); + (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); } else { /* Set map to ide */ - pci_write_config8(dev, SATA_MAP, - pci_read_config8(dev, SATA_MAP) & ~0xc3); + pci_write_config8(dev, SATA_MAP, pci_read_config8(dev, SATA_MAP) & ~0xc3); } /* At this point, the new pci id will appear on the bus */ } @@ -143,8 +138,7 @@ static void sata_init(struct device *dev) struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); if (ahci_res != NULL) /* write AHCI GHC_PI register */ - write32(res2mmio(ahci_res, 0xc, 0), - config->sata_ports_implemented); + write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented); break; default: case SATA_MODE_IDE_PLAIN: @@ -219,7 +213,7 @@ static void sata_init(struct device *dev) } static struct pci_operations sata_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations sata_ops = { diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index d533b8776a..b6c669af55 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -34,8 +34,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 data) return do_smbus_write_byte(res->base, device, address, data); } -static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, - const u8 *buf) +static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buf) { u16 device; struct resource *res; @@ -62,9 +61,9 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf) static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, - .block_read = lsmbus_block_read, - .block_write = lsmbus_block_write, + .write_byte = lsmbus_write_byte, + .block_read = lsmbus_block_read, + .block_write = lsmbus_block_write, }; static struct pci_operations smbus_pci_ops = { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index d19ee1191b..b5642e7b53 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -18,15 +18,11 @@ #include "nvs.h" -/* While we read PMBASE dynamically in case it changed, let's - * initialize it with a sane value - */ +/* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */ u16 pmbase = DEFAULT_PMBASE; u8 smm_initialized = 0; -/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located - * by coreboot. - */ +/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located by coreboot. */ global_nvs_t *gnvs = (global_nvs_t *)0x0; void southbridge_update_gnvs(u8 apm_cnt, int *smm_done) diff --git a/src/southbridge/intel/i82801gx/usb.c b/src/southbridge/intel/i82801gx/usb.c index 8a8b58cb88..d4b559a37b 100644 --- a/src/southbridge/intel/i82801gx/usb.c +++ b/src/southbridge/intel/i82801gx/usb.c @@ -31,7 +31,7 @@ static void usb_init(struct device *dev) } static struct pci_operations usb_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations usb_ops = { diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 0efae6daca..d127496cd6 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -46,8 +46,7 @@ static void usb_ehci_init(struct device *dev) printk(BIOS_DEBUG, "done.\n"); } -static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, - unsigned int device) +static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device) { u8 access_cntl; |