diff options
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 7 |
2 files changed, 9 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index c104cbb3b8..43f8bceb91 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -58,4 +58,8 @@ config FINALIZE_USB_ROUTE_XHCI If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback. +config PCIEXP_AER + bool + default y + endif diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 35ce5c4702..077dcd6573 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -670,8 +670,11 @@ static void pch_pcie_early(struct device *dev) /* Set EOI forwarding disable. */ pci_or_config32(dev, 0xd4, 1 << 1); - /* Set something involving advanced error reporting. */ - pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); + /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ + if (CONFIG(PCIEXP_AER)) + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001); + else + pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29)); if (is_lp) pci_or_config32(dev, 0x100, 1 << 29); |