diff options
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/chip.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index 89bbb1ce0c..12bb401f77 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -65,7 +65,7 @@ struct southbridge_intel_lynxpoint_config { uint32_t gen4_dec; /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; + bool pcie_port_coalesce; /* Force root port ASPM configuration with port bitmap */ uint8_t pcie_port_force_aspm; diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 5f21e619a5..30773e63b2 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -28,7 +28,7 @@ struct root_port_config { u32 b0d28f0_32c; u32 b0d28f4_32c; u32 b0d28f5_32c; - int coalesce; + bool coalesce; int gbe_port; int num_ports; struct device *ports[MAX_NUM_ROOT_PORTS]; @@ -304,7 +304,7 @@ static void root_port_commit_config(void) /* If the first root port is disabled the coalesce ports. */ if (!is_rp_enabled(1)) - rpc.coalesce = 1; + rpc.coalesce = true; /* Perform clock gating configuration. */ pcie_enable_clock_gating(); |