diff options
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/sleepstates.asl | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 31 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_lpc.c | 54 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_smi.c | 39 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_smihandler.c | 75 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx_usb.c | 4 |
6 files changed, 175 insertions, 38 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl index 863eee72dd..06bfcb6a58 100644 --- a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl +++ b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl @@ -19,9 +19,9 @@ * MA 02110-1301 USA */ -Name(\_S0, Package(){0x0,0x0,0,0}) -Name(\_S1, Package(){0x1,0x0,0,0}) -Name(\_S3, Package(){0x5,0x0,0,0}) -Name(\_S4, Package(){0x6,0x0,0,0}) -Name(\_S5, Package(){0x7,0x0,0,0}) +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +// Name(\_S1, Package(){0x1,0x1,0x0,0x0}) +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +Name(\_S4, Package(){0x6,0x6,0x0,0x0}) +Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 5c29c9ea62..8f62c1be2c 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -32,6 +32,8 @@ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 + +#define IO_APIC_ADDR 0xfec00000 #define HPET_ADDR 0xfed00000 #define DEFAULT_RCBA 0xfed1c000 @@ -276,7 +278,20 @@ extern void i82801gx_enable(device_t dev); /* ICH7 PMBASE */ #define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 #define SLP_EN (1 << 13) #define SLP_TYP (7 << 10) @@ -290,8 +305,24 @@ extern void i82801gx_enable(device_t dev); #define LV4 0x16 #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 +#define USB4_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) #define GPE0_EN 0x2c #define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) #define SMI_EN 0x30 #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c index a99e50e61e..be3eee68c5 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c +++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c @@ -40,8 +40,8 @@ static void i82801gx_enable_apic(struct device *dev) { int i; u32 reg32; - volatile u32 *ioapic_index = (volatile u32 *)0xfec00000; - volatile u32 *ioapic_data = (volatile u32 *)0xfec00010; + volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); /* Enable ACPI I/O and power management. * Set SCI IRQ to IRQ9 @@ -175,7 +175,7 @@ static void i82801gx_power_options(device_t dev) u8 reg8; u16 reg16, pmbase; u32 reg32; - char *state; + const char *state; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -238,9 +238,13 @@ static void i82801gx_power_options(device_t dev) /* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */ reg16 = pci_read_config16(dev, GEN_PMCON_1); - reg16 &= ~((3 << 0) | (1 << 10)); - reg16 |= (1 << 3) | (1 << 5); - reg16 |= (1 << 2); // CLKRUN_EN + reg16 &= ~(3 << 0); // SMI# rate 1 minute + reg16 |= (1 << 2); // CLKRUN_EN - Mobile/Ultra only + reg16 |= (1 << 3); // Speedstep Enable - Mobile/Ultra only + reg16 |= (1 << 5); // CPUSLP_EN Desktop only + // another laptop wants this? + // reg16 &= ~(1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only + reg16 |= (1 << 10); // BIOS_PCI_EXP_EN - Desktop/Mobile only #if DEBUG_PERIODIC_SMIS /* Set DEBUG_PERIODIC_SMIS in i82801gx.h to debug using * periodic SMIs. @@ -259,15 +263,10 @@ static void i82801gx_power_options(device_t dev) /* Set up power management block and determine sleep mode */ reg32 = inl(pmbase + 0x04); // PM1_CNT -#if 0 -#if CONFIG_HAVE_ACPI_RESUME - acpi_slp_type = (((reg32 >> 10) & 7) == 5) ? 3 : 0; - printk_debug("PM1_CNT: 0x%08x --> acpi_sleep_type: %x\n", - reg32, acpi_slp_type); -#endif -#endif - reg32 |= (1 << 1); // enable C3->C0 transition on bus master - reg32 |= 1; // SCI_EN + + reg32 &= ~(7 << 10); // SLP_TYP + reg32 |= (1 << 1); // enable C3->C0 transition on bus master + reg32 |= (1 << 0); // SCI_EN outl(reg32, pmbase + 0x04); } @@ -308,10 +307,10 @@ static void enable_hpet(void) u32 reg32; /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(0x3404); + reg32 = RCBA32(HPTC); reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); - RCBA32(0x3404) = reg32; + RCBA32(HPTC) = reg32; } static void enable_clock_gating(void) @@ -319,16 +318,18 @@ static void enable_clock_gating(void) u32 reg32; /* Enable Clock Gating for most devices */ - reg32 = RCBA32(0x341c); + reg32 = RCBA32(CG); reg32 |= (1 << 31); // LPC clock gating reg32 |= (1 << 30); // PATA clock gating // SATA clock gating reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); reg32 |= (1 << 23); // AC97 clock gating - reg32 |= (1 << 20) | (1 << 19); // USB EHCI clock gating + reg32 |= (1 << 19); // USB EHCI clock gating reg32 |= (1 << 3) | (1 << 1); // DMI clock gating reg32 |= (1 << 2); // PCIe clock gating; - RCBA32(0x341c) = reg32; + reg32 &= ~(1 << 20); // No static clock gating for USB + reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating + RCBA32(CG) = reg32; } #if CONFIG_HAVE_SMI_HANDLER @@ -392,10 +393,16 @@ static void i82801gx_spi_init(void) RCBA16(SPIBASE + 2) = spicontrol; } -static void i82801gx_fixups(void) +static void i82801gx_fixups(struct device *dev) { /* This needs to happen after PCI enumeration */ RCBA32(0x1d40) |= 1; + + /* USB Transient Disconnect Detect: + * Prevent a SE0 condition on the USB ports from being + * interpreted by the UHCI controller as a disconnect + */ + pci_write_config8(dev, 0xad, 0x3); } static void lpc_init(struct device *dev) @@ -437,7 +444,8 @@ static void lpc_init(struct device *dev) setup_i8259(); /* The OS should do this? */ - // i8259_configure_irq_trigger(9, 1); + /* Interrupt 9 should be level triggered (SCI) */ + i8259_configure_irq_trigger(9, 1); #if CONFIG_HAVE_SMI_HANDLER i82801gx_lock_smm(dev); @@ -445,7 +453,7 @@ static void lpc_init(struct device *dev) i82801gx_spi_init(); - i82801gx_fixups(); + i82801gx_fixups(dev); } static void i82801gx_lpc_read_resources(device_t dev) diff --git a/src/southbridge/intel/i82801gx/i82801gx_smi.c b/src/southbridge/intel/i82801gx/i82801gx_smi.c index 7fb4abfdaa..7187b1af91 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smi.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smi.c @@ -155,6 +155,34 @@ static void dump_gpe0_status(u32 gpe0_sts) printk_debug("\n"); } + +/** + * @brief read and clear ALT_GP_SMI_STS + * @return ALT_GP_SMI_STS register + */ +static u16 reset_alt_gp_smi_status(void) +{ + u16 reg16; + + reg16 = inl(pmbase + ALT_GP_SMI_STS); + /* set status bits are cleared by writing 1 to them */ + outl(reg16, pmbase + ALT_GP_SMI_STS); + + return reg16; +} + +static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts) +{ + int i; + printk_debug("ALT_GP_SMI_STS: "); + for (i=15; i<= 0; i--) { + if (alt_gp_smi_sts & (1 << i)) printk_debug("GPI%d ", (i-16)); + } + printk_debug("\n"); +} + + + /** * @brief read and clear TCOx_STS * @return TCOx_STS registers @@ -212,6 +240,7 @@ extern uint8_t smm_relocation_start, smm_relocation_end; void smm_relocate(void) { u32 smi_en; + u16 pm1_en; printk_debug("Initializing SMM handler..."); @@ -232,6 +261,7 @@ void smm_relocate(void) dump_smi_status(reset_smi_status()); dump_pm1_status(reset_pm1_status()); dump_gpe0_status(reset_gpe0_status()); + dump_alt_gp_smi_status(reset_alt_gp_smi_status()); dump_tco_status(reset_tco_status()); /* Enable SMI generation: @@ -244,6 +274,10 @@ void smm_relocate(void) */ smi_en = 0; /* reset SMI enables */ + +#if 0 + smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN; +#endif smi_en |= TCO_EN; smi_en |= APMC_EN; #if DEBUG_PERIODIC_SMIS @@ -260,6 +294,11 @@ void smm_relocate(void) outl(smi_en, pmbase + SMI_EN); + pm1_en = 0; + pm1_en |= PWRBTN_EN; + pm1_en |= GBL_EN; + outw(pm1_en, pmbase + PM1_EN); + /** * There are several methods of raising a controlled SMI# via * software, among them: diff --git a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c index 8cf39e8ded..cf44772d9f 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_smihandler.c +++ b/src/southbridge/intel/i82801gx/i82801gx_smihandler.c @@ -25,14 +25,15 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#include <device/pci_def.h> #include "i82801gx.h" #include "i82801gx_power.h" #define DEBUG_SMI #define APM_CNT 0xb2 -#define CST_CONTROL 0x85 // 0x85 crashes the box -#define PST_CONTROL 0x80 // 0x80 crashes the box +#define CST_CONTROL 0x85 +#define PST_CONTROL 0x80 #define ACPI_DISABLE 0x1e #define ACPI_ENABLE 0xe1 #define GNVS_UPDATE 0xea @@ -88,6 +89,8 @@ static void dump_pm1_status(u16 pm1_sts) if (pm1_sts & (1 << 4)) printk_spew("BM "); if (pm1_sts & (1 << 0)) printk_spew("TMROF "); printk_spew("\n"); + int reg16 = inw(pmbase + PM1_EN); + printk_spew("PM1_EN: %x\n", reg16); } /** @@ -245,6 +248,41 @@ void southbridge_smi_set_eos(void) outb(reg8, pmbase + SMI_EN); } +static void busmaster_disable_on_bus(int bus) +{ + int slot, func; + unsigned int val; + unsigned char hdr; + + for (slot = 0; slot < 0x20; slot++) { + for (func = 0; func < 8; func++) { + u32 reg32; + device_t dev = PCI_DEV(bus, slot, func); + + val = pci_read_config32(dev, PCI_VENDOR_ID); + + if (val == 0xffffffff || val == 0x00000000 || + val == 0x0000ffff || val == 0xffff0000) + continue; + + /* Disable Bus Mastering for this one device */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~PCI_COMMAND_MASTER; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* If this is a bridge, then follow it. */ + hdr = pci_read_config8(dev, PCI_HEADER_TYPE); + hdr &= 0x7f; + if (hdr == PCI_HEADER_TYPE_BRIDGE || + hdr == PCI_HEADER_TYPE_CARDBUS) { + unsigned int buses; + buses = pci_read_config32(dev, PCI_PRIMARY_BUS); + busmaster_disable_on_bus((buses >> 8) & 0xff); + } + } + } +} + static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save) { @@ -281,12 +319,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat case 6: printk_debug("SMI#: Entering S4 (Suspend-To-Disk)\n"); break; case 7: printk_debug("SMI#: Entering S5 (Soft Power off)\n"); -#if 0 - /* Set PME_B0_EN before going to S5 */ - reg32 = inl(pmbase + GPE0_EN); - reg32 |= PME_B0_EN; - outl(reg32, pmbase + GPE0_EN); -#endif + + outl(0, pmbase + GPE0_EN); + /* Should we keep the power state after a power loss? * In case the setting is "ON" or "OFF" we don't have * to do anything. But if it's "KEEP" we have to switch @@ -297,6 +332,9 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat reg8 |= 1; pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); } + + /* also iterates over all bridges on bus 0 */ + busmaster_disable_on_bus(0); break; default: printk_debug("SMI#: ERROR: SLP_TYP reserved\n"); break; } @@ -376,6 +414,16 @@ static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_ pm1_sts = reset_pm1_status(); dump_pm1_status(pm1_sts); + + /* While OSPM is not active, poweroff immediately + * on a power button event. + */ + if (pm1_sts & PWRBTN_STS) { + // power button pressed + u32 reg32; + reg32 = (7 << 10) | (1 << 13); + outl(reg32, pmbase + PM1_CNT); + } } static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save) @@ -386,6 +434,8 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state dump_gpe0_status(gpe0_sts); } +void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts); + static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) { u16 reg16; @@ -393,8 +443,13 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ outl(reg16, pmbase + ALT_GP_SMI_STS); reg16 &= inw(pmbase + ALT_GP_SMI_EN); - if (reg16) - printk_debug("GPI (mask %04x)\n",reg16); + + if (mainboard_smi_gpi) { + mainboard_smi_gpi(reg16); + } else { + if (reg16) + printk_debug("GPI (mask %04x)\n",reg16); + } } static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb.c b/src/southbridge/intel/i82801gx/i82801gx_usb.c index a753202f72..2803f9cdef 100644 --- a/src/southbridge/intel/i82801gx/i82801gx_usb.c +++ b/src/southbridge/intel/i82801gx/i82801gx_usb.c @@ -35,6 +35,10 @@ static void usb_init(struct device *dev) reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + // Erratum + pci_write_config8(dev, 0xca, 0x00); + + // Yes. Another Erratum reg8 = pci_read_config8(dev, 0xca); reg8 |= (1 << 0); pci_write_config8(dev, 0xca, reg8); |