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Diffstat (limited to 'src/southbridge/intel/i82801gx/acpi')
-rw-r--r--src/southbridge/intel/i82801gx/acpi/globalnvs.asl12
-rw-r--r--src/southbridge/intel/i82801gx/acpi/ich7.asl74
-rw-r--r--src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl41
-rw-r--r--src/southbridge/intel/i82801gx/acpi/ich7_pci.asl2
-rw-r--r--src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl12
-rw-r--r--src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl8
-rw-r--r--src/southbridge/intel/i82801gx/acpi/sleepstates.asl10
7 files changed, 105 insertions, 54 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index 5ac1c83cd6..0384376417 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -81,7 +81,16 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
PPCM, 8, // 0x2c - Max. PPC state
/* Super I/O & CMOS config */
Offset (0x32),
- NATP, 8, // 0x32 - ...
+ NATP, 8, // 0x32 -
+ CMAP, 8, // 0x33 -
+ CMBP, 8, // 0x34 -
+ LPTP, 8, // 0x35 - LPT Port
+ FDCP, 8, // 0x36 - Floppy Disk Controller
+ RFDV, 8, // 0x37 -
+ HOTK, 8, // 0x38 -
+ RTCF, 8, // 0x39 -
+ UTIL, 8, // 0x3a -
+ ACIN, 8, // 0x3b -
/* Integrated Graphics Device */
Offset (0x3c),
IGDS, 8, // 0x3c - IGD state (primary = 1)
@@ -158,4 +167,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
/* Mainboard Specific (TODO move elsewhere) */
Offset (0xf0),
DOCK, 8, // 0xf0 - Docking Status
+ BTEN, 8, // 0xf1 - Bluetooth Enable
}
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl
index 3f845c483b..a37208c021 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl
@@ -19,8 +19,7 @@
* MA 02110-1301 USA
*/
-/* Intel i82801G support
- */
+/* Intel 82801Gx support */
Scope(\)
{
@@ -34,10 +33,7 @@ Scope(\)
}
// ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
- // this doesn't work as ACPI initializes regions and packages first, devices second.
- // use dynamic operation region? if so, how? XXX
- //OperationRegion(PMIO, SystemIO, And(\_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80)
- OperationRegion(PMIO, SystemIO, 0x500, 0x80)
+ OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
Field(PMIO, ByteAcc, NoLock, Preserve)
{
Offset(0x42), // General Purpose Control
@@ -49,7 +45,7 @@ Scope(\)
}
// ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
- OperationRegion(GPIO, SystemIO, 0x1180, 0x3c)
+ OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x3c)
Field(GPIO, ByteAcc, NoLock, Preserve)
{
Offset(0x00), // GPIO Use Select
@@ -63,12 +59,32 @@ Scope(\)
GIO2, 8,
GIO3, 8,
Offset(0x0c), // GPIO Level
- GL00, 8,
- GL01, 8,
- , 3,
- GP27, 1, // SATA_PWR_EN #0
- GP28, 1, // SATA_PWR_EN #1
- , 3,
+ GL00, 6,
+ GP07, 1, // GDET
+ GP08, 1,
+ GP09, 1,
+ GP10, 1, // HPMU
+ GP11, 1, // GPSE
+ GP12, 1,
+ GP13, 1, // WLED
+ GP14, 1, // BLED
+ GP15, 1, // GLED
+ GP16, 1, // GDIS
+ GP17, 1,
+ GP18, 1,
+ GP19, 1, // SPCI
+ GP20, 1, // TSDT
+ GP21, 1, // SCPU
+ GP22, 1,
+ GP23, 1,
+ GP24, 1, // LANP
+ GP25, 1, // DKLR
+ GP26, 1, // WLAN
+ GP27, 1, // SATA_PWR_EN #0 / SPOF
+ GP28, 1, // SATA_PWR_EN #1 / SPMU
+ GP29, 1,
+ GP30, 1,
+ GP31, 1,
Offset(0x18), // GPIO Blink
GB00, 8,
GB01, 8,
@@ -90,10 +106,14 @@ Scope(\)
GIO6, 8,
GIO7, 8,
Offset(0x38), // GPIO Level 2
- , 5,
- GP37, 1, // PATA_PWR_EN
- GP38, 1, // Battery / Power (?)
- GP39, 1, // ??
+ GP32, 1,
+ GP33, 1, // CREN
+ GP34, 1, // CRRS
+ GP35, 1,
+ GP36, 1, // STAD
+ GP37, 1, // PATA_PWR_EN / HDDE
+ GP38, 1, // Battery / Power (?) / MB00
+ GP39, 1, // ?? / MB01
GL05, 8,
GL06, 8,
GL07, 8
@@ -101,7 +121,7 @@ Scope(\)
// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
- OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000)
+ OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
Field(RCRB, DWordAcc, Lock, Preserve)
{
Offset(0x0000), // Backbone
@@ -139,30 +159,30 @@ Scope(\)
}
// 0:1b.0 High Definition Audio (Azalia)
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_audio.asl"
// PCI Express Ports
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_pcie.asl"
// USB
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_usb.asl"
// PCI Bridge
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_pci.asl"
// AC97 Audio and Modem
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_ac97.asl"
// LPC Bridge
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_lpc.asl"
// PATA
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_pata.asl"
// SATA
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_sata.asl"
// SMBus
-Include ("../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl")
+#include "../../../southbridge/intel/i82801gx/acpi/ich7_smbus.asl"
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
index fdf05b2e2f..a18673c679 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_lpc.asl
@@ -51,9 +51,9 @@ Device (LPCB)
RCBA, 18,
}
- Include ("../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl")
+ #include "../../../southbridge/intel/i82801gx/acpi/ich7_irqlinks.asl"
- Include ("acpi/ec.asl")
+ #include "acpi/ec.asl"
Device (DMAC) // DMA Controller
{
@@ -174,11 +174,9 @@ Device (LPCB)
IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
- // IO (Decode16, 0x680, 0x680, 0x1, 0x70) // IO ???
IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
- IO (Decode16, 0x0500, 0x0500, 0x1, 0x80) // ICH7-M ACPI
- IO (Decode16, 0x0480, 0x0480, 0x1, 0x40) // ICH7-M GPIO
- // IO (Decode16, 0x1640, 0x1640, 0x1, 0x10) // IO ???
+ IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI
+ IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO
})
}
@@ -188,7 +186,8 @@ Device (LPCB)
Name (_CRS, ResourceTemplate()
{
IO (Decode16, 0x70, 0x70, 1, 8)
- IRQNoFlags() { 8 }
+// Disable as Windows doesn't like it, and systems don't seem to use it.
+// IRQNoFlags() { 8 }
})
}
@@ -203,7 +202,31 @@ Device (LPCB)
})
}
- Include ("acpi/superio.asl")
+ #include "acpi/superio.asl"
+
+#ifdef ENABLE_TPM
+ Device (TPM) // Trusted Platform Module
+ {
+ Name(_HID, EISAID("IFX0102"))
+ Name(_CID, 0x310cd041)
+ Name(_UID, 1)
+
+ Method(_STA, 0)
+ {
+ If (TPMP) {
+ Return (0xf)
+ }
+ Return (0x0)
+ }
+
+ Name(_CRS, ResourceTemplate() {
+ IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
+ IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
+ IRQ (Edge, Activehigh, Exclusive) { 6 }
+ })
+ }
+#endif
Device (PS2K) // Keyboard
{
@@ -237,6 +260,7 @@ Device (LPCB)
}
}
+#ifdef ENABLE_FDC
Device (FDC0) // Floppy controller
{
Name (_HID, EisaId ("PNP0700"))
@@ -262,4 +286,5 @@ Device (LPCB)
})
}
+#endif
}
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
index 9bcf58e413..d253d51a78 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_pci.asl
@@ -70,7 +70,7 @@ Device (PCIB)
Method (_PRT)
{
- Include ("acpi/ich7_pci_irqs.asl")
+ #include "acpi/ich7_pci_irqs.asl"
}
}
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl b/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
index 0822e8ee02..a76c7fbe4d 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_pcie.asl
@@ -26,7 +26,7 @@
Device (RP01)
{
NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -52,7 +52,7 @@ Device (RP01)
Device (RP02)
{
NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -79,7 +79,7 @@ Device (RP02)
Device (RP03)
{
NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -106,7 +106,7 @@ Device (RP03)
Device (RP04)
{
NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -133,7 +133,7 @@ Device (RP04)
Device (RP05)
{
NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -160,7 +160,7 @@ Device (RP05)
Device (RP06)
{
NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //Include ("pcie_port.asl")
+ //#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
diff --git a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
index b7d807ee44..b6d2d6a2ab 100644
--- a/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
+++ b/src/southbridge/intel/i82801gx/acpi/ich7_smbus.asl
@@ -33,7 +33,6 @@ Device (SBUS)
I2CE, 1
}
- /*
OperationRegion (SMBI, SystemIO, 0x400, 0x20)
Field (SMBI, ByteAcc, NoLock, Preserve)
{
@@ -59,6 +58,7 @@ Device (SBUS)
NDLH, 8, // Notify Data High Byte
}
+#ifdef ENABLE_SMBUS_METHODS
// Kill all SMBus communication
Method (KILL, 0, Serialized)
{
@@ -237,10 +237,6 @@ Device (SBUS)
Return (0xffff)
}
- */
-
- // Todo: Does anyone ever use these?
- // Missing: Read / Write Word
- // Missing: Read / Write Block
+#endif
}
diff --git a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl
index 61595854b2..863eee72dd 100644
--- a/src/southbridge/intel/i82801gx/acpi/sleepstates.asl
+++ b/src/southbridge/intel/i82801gx/acpi/sleepstates.asl
@@ -19,9 +19,9 @@
* MA 02110-1301 USA
*/
-Name(\_S0, Package(4){0x0,0x0,0,0})
-Name(\_S1, Package(4){0x1,0x0,0,0})
-Name(\_S3, Package(4){0x5,0x0,0,0})
-Name(\_S4, Package(4){0x6,0x0,0,0})
-Name(\_S5, Package(4){0x7,0x0,0,0})
+Name(\_S0, Package(){0x0,0x0,0,0})
+Name(\_S1, Package(){0x1,0x0,0,0})
+Name(\_S3, Package(){0x5,0x0,0,0})
+Name(\_S4, Package(){0x6,0x0,0,0})
+Name(\_S5, Package(){0x7,0x0,0,0})
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 01:15:53 +0000