diff options
Diffstat (limited to 'src/southbridge/intel/i3100/i3100_early_smbus.c')
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_early_smbus.c | 43 |
1 files changed, 0 insertions, 43 deletions
diff --git a/src/southbridge/intel/i3100/i3100_early_smbus.c b/src/southbridge/intel/i3100/i3100_early_smbus.c deleted file mode 100644 index 79825d153a..0000000000 --- a/src/southbridge/intel/i3100/i3100_early_smbus.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * - */ - -#include "i3100_smbus.h" - -#define SMBUS_IO_BASE 0x0f00 - -static void enable_smbus(void) -{ - device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - - print_spew("SMBus controller enabled\n"); - pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - pci_write_config8(dev, 0x40, 1); - pci_write_config8(dev, 0x4, 1); - /* SMBALERT_DIS */ - outb(4, SMBUS_IO_BASE + SMBSLVCMD); - - /* Disable interrupt generation */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); -} - -static int smbus_read_byte(u32 device, u32 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} |