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Diffstat (limited to 'src/southbridge/intel/fsp_rangeley/Kconfig')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/Kconfig | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig new file mode 100644 index 0000000000..2c8ceacd9a --- /dev/null +++ b/src/southbridge/intel/fsp_rangeley/Kconfig @@ -0,0 +1,63 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config SOUTHBRIDGE_INTEL_FSP_RANGELEY + bool + +if SOUTHBRIDGE_INTEL_FSP_RANGELEY + +config SOUTH_BRIDGE_OPTIONS # dummy + def_bool y + select IOAPIC + select HAVE_HARD_RESET + select HAVE_USBDEBUG + select USE_WATCHDOG_ON_BOOT + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select SPI_FLASH + select HAVE_INTEL_FIRMWARE + +config EHCI_BAR + hex + default 0xfef00000 + +config EHCI_DEBUG_OFFSET + hex + default 0xa0 + +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +config HPET_MIN_TICKS + hex + default 0x80 + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "../intel/mainboard/intel/rangeley" + help + The path and filename to the descriptor.bin file. + +endif |