diff options
Diffstat (limited to 'src/southbridge/intel/fsp_bd82x6x/Kconfig')
| -rw-r--r-- | src/southbridge/intel/fsp_bd82x6x/Kconfig | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig deleted file mode 100644 index 85c6ee7862..0000000000 --- a/src/southbridge/intel/fsp_bd82x6x/Kconfig +++ /dev/null @@ -1,57 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Google Inc. -## Copyright (C) 2013 Sage Electronic Engineering, LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc. -## - -config SOUTHBRIDGE_INTEL_FSP_BD82X6X - bool - -if SOUTHBRIDGE_INTEL_FSP_BD82X6X - -config SOUTH_BRIDGE_OPTIONS # dummy - def_bool y - select IOAPIC - select HAVE_HARD_RESET - select HAVE_SMI_HANDLER - select USE_WATCHDOG_ON_BOOT - select PCIEXP_ASPM - select PCIEXP_COMMON_CLOCK - select SPI_FLASH - select COMMON_FADT - select HAVE_INTEL_FIRMWARE - -config EHCI_BAR - hex - default 0xfef00000 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/fsp_bd82x6x/bootblock.c" - -config SERIRQ_CONTINUOUS_MODE - bool - default n - help - If you set this option to y, the serial IRQ machine will be - operated in continuous mode. - -config HPET_MIN_TICKS - hex - default 0x80 - -endif |