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-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c9
2 files changed, 7 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index c24c71c30f..9eb3111661 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -39,6 +39,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select HAVE_INTEL_FIRMWARE
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select RTC
+ select HAVE_INTEL_CHIPSET_LOCKDOWN
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index ca26250808..901f71be18 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -829,9 +829,12 @@ static void southbridge_fill_ssdt(device_t device)
static void lpc_final(struct device *dev)
{
- if (CONFIG_HAVE_SMI_HANDLER && acpi_is_wakeup_s3()) {
- /* Call SMM finalize() handlers before resume */
- outb(0xcb, 0xb2);
+ /* Call SMM finalize() handlers before resume */
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ if (IS_ENABLED(CONFIG_INTEL_CHIPSET_LOCKDOWN) ||
+ acpi_is_wakeup_s3()) {
+ outb(APM_CNT_FINALIZE, APM_CNT);
+ }
}
}