diff options
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_usb.c | 2 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 8fc72b8670..607cd14911 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -168,8 +168,8 @@ int intel_early_me_init_done(u8 status) } else if ((me_fws2 & 0x100) == 0x100) { if ((me_fws2 & 0x80) == 0x80) { printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n"); - reg16 = pcie_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; - pcie_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); + reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; + pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16); set_global_reset(0); outb(0x6, 0xcf9); halt(); diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 21a996debf..cf0ea17cd2 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -285,8 +285,8 @@ init_dmi (void) void early_pch_init_native (void) { - pcie_write_config8 (SOUTHBRIDGE, 0xa6, - pcie_read_config8 (SOUTHBRIDGE, 0xa6) | 2); + pci_write_config8 (SOUTHBRIDGE, 0xa6, + pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); write32 (DEFAULT_RCBA + 0x2088, 0x00109000); read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index aa9b5fc88c..81d3b6b505 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -66,7 +66,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) for (i = 0; i < 22; i++) write32 (DEFAULT_RCBABASE + (0x35a8 + 4 * i), 0); - pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); + pci_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000); /* Relock registers. */ outw (0x0000, DEFAULT_PMBASE | 0x003c); |