diff options
Diffstat (limited to 'src/southbridge/intel/bd82x6x')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 5 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index e4e002d805..8433bb2dd5 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -17,6 +17,7 @@ #include "chip.h" #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) +#define PCI_DEVICE_ID_INTEL_UM77 0x1e58 static void wait_iobp(void) { @@ -135,8 +136,15 @@ void early_pch_init_native_dmi_post(void) void early_pch_init_native(void) { + const u16 dev_id = pci_read_config16(PCH_LPC_DEV, PCI_DEVICE_ID); + u8 pcie_ports = (dev_id == PCI_DEVICE_ID_INTEL_UM77) ? 4 : 8; + pci_write_config8(SOUTHBRIDGE, 0xa6, pci_read_config8(SOUTHBRIDGE, 0xa6) | 2); + /* Clear this bit early for PCIe device detection */ + for (uint8_t i = 0; i < pcie_ports; i++) + pci_update_config32(PCH_PCIE_DEV(i), 0x338, ~(1 << 26), 0); + RCBA32(CIR1) = 0x00109000; RCBA32(REC); // !!! = 0x00000000 RCBA32(REC) = 0x40000000; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 8face0649e..6d164ead42 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -74,12 +74,15 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) #define PCH_THERMAL_DEV PCI_DEV(0, 0x1f, 6) -#define PCH_PCIE_DEV_SLOT 28 #define PCH_IOAPIC_PCI_BUS 250 #define PCH_IOAPIC_PCI_SLOT 31 #define PCH_HPET_PCI_BUS 250 #define PCH_HPET_PCI_SLOT 15 +/* PCI Configuration Space (D28:F0): PCI2PCI */ +#define PCH_PCIE_DEV_SLOT 28 +#define PCH_PCIE_DEV(_func) PCI_DEV(0, PCH_PCIE_DEV_SLOT, _func) + /* PCI Configuration Space (D20:F0): xHCI */ #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) |