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path: root/src/southbridge/intel/bd82x6x/usb_xhci.c
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Diffstat (limited to 'src/southbridge/intel/bd82x6x/usb_xhci.c')
-rw-r--r--src/southbridge/intel/bd82x6x/usb_xhci.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 19c419facb..eb89a7d64f 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -29,6 +29,7 @@
static void usb_xhci_init(struct device *dev)
{
u32 reg32;
+ struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
printk(BIOS_DEBUG, "XHCI: Setting up controller.. ");
@@ -37,6 +38,9 @@ static void usb_xhci_init(struct device *dev)
reg32 |= 1;
pci_write_config32(dev, 0x44, reg32);
+ pci_write_config32(dev, 0xd4, config->xhci_switchable_ports);
+ pci_write_config32(dev, 0xdc, config->superspeed_capable_ports);
+
/* Enable clock gating */
reg32 = pci_read_config32(dev, 0x40);
reg32 &= ~((1 << 20) | (1 << 21));