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-rw-r--r--src/southbridge/amd/cimx/Kconfig1
-rw-r--r--src/southbridge/amd/cimx/Makefile.inc3
-rw-r--r--src/southbridge/amd/cimx/sb700/Amd.h359
-rw-r--r--src/southbridge/amd/cimx/sb700/AmdSbLib.h80
-rw-r--r--src/southbridge/amd/cimx/sb700/Kconfig66
-rw-r--r--src/southbridge/amd/cimx/sb700/Makefile.inc34
-rw-r--r--src/southbridge/amd/cimx/sb700/Platform.h85
-rw-r--r--src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h38
-rw-r--r--src/southbridge/amd/cimx/sb700/amd_pci_int_types.h25
-rw-r--r--src/southbridge/amd/cimx/sb700/bootblock.c59
-rw-r--r--src/southbridge/amd/cimx/sb700/chip.h36
-rw-r--r--src/southbridge/amd/cimx/sb700/early.c91
-rw-r--r--src/southbridge/amd/cimx/sb700/gpio_oem.h54
-rw-r--r--src/southbridge/amd/cimx/sb700/late.c307
-rw-r--r--src/southbridge/amd/cimx/sb700/lpc.c180
-rw-r--r--src/southbridge/amd/cimx/sb700/lpc.h28
-rw-r--r--src/southbridge/amd/cimx/sb700/ramtop.c43
-rw-r--r--src/southbridge/amd/cimx/sb700/reset.c58
-rw-r--r--src/southbridge/amd/cimx/sb700/sb_cimx.h44
-rw-r--r--src/southbridge/amd/cimx/sb700/smbus.c256
-rw-r--r--src/southbridge/amd/cimx/sb700/smbus.h78
-rw-r--r--src/southbridge/amd/cimx/sb700/smbus_spd.c160
-rw-r--r--src/southbridge/amd/cimx/sb700/smbus_spd.h61
-rw-r--r--src/southbridge/amd/common/Makefile.inc1
24 files changed, 0 insertions, 2147 deletions
diff --git a/src/southbridge/amd/cimx/Kconfig b/src/southbridge/amd/cimx/Kconfig
index cca87b0660..06544938a7 100644
--- a/src/southbridge/amd/cimx/Kconfig
+++ b/src/southbridge/amd/cimx/Kconfig
@@ -17,6 +17,5 @@ config AMD_SB_CIMX
bool
default n
-source src/southbridge/amd/cimx/sb700/Kconfig
source src/southbridge/amd/cimx/sb800/Kconfig
source src/southbridge/amd/cimx/sb900/Kconfig
diff --git a/src/southbridge/amd/cimx/Makefile.inc b/src/southbridge/amd/cimx/Makefile.inc
index b308e90190..b70d2feb7f 100644
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -13,14 +13,11 @@
# GNU General Public License for more details.
#
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += sb700
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900
-romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c
diff --git a/src/southbridge/amd/cimx/sb700/Amd.h b/src/southbridge/amd/cimx/sb700/Amd.h
deleted file mode 100644
index 2e5702a061..0000000000
--- a/src/southbridge/amd/cimx/sb700/Amd.h
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _AMD_H_
-#define _AMD_H_
-
-// AGESA Types and Definitions
-#ifndef NULL
-#define NULL 0
-#endif
-
-#define LAST_ENTRY 0xFFFFFFFF
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-#define IN
-#define OUT
-
-#ifndef Int16FromChar
-#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
-#endif
-#ifndef Int32FromChar
-#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
-#endif
-
-#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
-
-typedef unsigned int AGESA_STATUS;
-
-#define AGESA_SUCCESS ((AGESA_STATUS) 0x0)
-#define AGESA_ALERT ((AGESA_STATUS) 0x40000000)
-#define AGESA_WARNING ((AGESA_STATUS) 0x40000001)
-#define AGESA_UNSUPPORTED ((AGESA_STATUS) 0x80000003)
-#define AGESA_ERROR ((AGESA_STATUS) 0xC0000001)
-#define AGESA_CRITICAL ((AGESA_STATUS) 0xC0000002)
-#define AGESA_FATAL ((AGESA_STATUS) 0xC0000003)
-
-typedef AGESA_STATUS (*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2, void* ConfigPtr);
-typedef AGESA_STATUS (*IMAGE_ENTRY) (IN OUT void* ConfigPtr);
-typedef AGESA_STATUS (*MODULE_ENTRY) (IN OUT void* ConfigPtr);
-
-///This allocation type is used by the AmdCreateStruct entry point
-typedef enum {
- PreMemHeap = 0, ///< Create heap in cache.
- PostMemDram, ///< Create heap in memory.
- ByHost ///< Create heap by Host.
-} ALLOCATION_METHOD;
-
-/// These width descriptors are used by the library function, and others, to specify the data size
-typedef enum ACCESS_WIDTH {
- AccessWidth8 = 1, ///< Access width is 8 bits.
- AccessWidth16, ///< Access width is 16 bits.
- AccessWidth32, ///< Access width is 32 bits.
- AccessWidth64, ///< Access width is 64 bits.
-
- AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
- AccessS3SaveWidth16, ///< Save 16 bits data.
- AccessS3SaveWidth32, ///< Save 32 bits data.
- AccessS3SaveWidth64, ///< Save 64 bits data.
-} ACCESS_WIDTH;
-
-// AGESA Structures
-
-/// The standard header for all AGESA services.
-typedef struct _AMD_CONFIG_PARAMS {
- IN unsigned int ImageBasePtr; ///< The AGESA Image base address.
- IN unsigned int Func; ///< The service desired, @sa dispatch.h.
- IN unsigned int AltImageBasePtr; ///< Alternate Image location
- IN unsigned int PcieBasePtr; ///< PCIe MMIO Base address, if configured.
- union { ///< Callback pointer
- IN unsigned long long PlaceHolder; ///< Place holder
- IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
- } CALLBACK;
- IN OUT unsigned int Reserved[2]; ///< This space is reserved for future use.
-} AMD_CONFIG_PARAMS;
-
-
-/// AGESA Binary module header structure
-typedef struct _AMD_IMAGE_HEADER {
- IN unsigned int Signature; ///< Binary Signature
- IN signed char CreatorID[8]; ///< 8 characters ID
- IN signed char Version[12]; ///< 12 characters version
- IN unsigned int ModuleInfoOffset; ///< Offset of module
- IN unsigned int EntryPointAddress; ///< Entry address
- IN unsigned int ImageBase; ///< Image base
- IN unsigned int RelocTableOffset; ///< Relocate Table offset
- IN unsigned int ImageSize; ///< Size
- IN unsigned short Checksum; ///< Checksum
- IN unsigned char ImageType; ///< Type
- IN unsigned char V_Reserved; ///< Reserved
-} AMD_IMAGE_HEADER;
-
-/// AGESA Binary module header structure
-typedef struct _AMD_MODULE_HEADER {
- IN unsigned int ModuleHeaderSignature; ///< Module signature
- IN signed char ModuleIdentifier[8]; ///< 8 characters ID
- IN signed char ModuleVersion[12]; ///< 12 characters version
- IN MODULE_ENTRY ModuleDispatcherPtr; ///< A pointer point to dispatcher
- IN struct _AMD_MODULE_HEADER *NextBlockPtr; ///< Next module header link
-} AMD_MODULE_HEADER;
-
-#define FUNC_0 0 // bit-placed for PCI address creation
-#define FUNC_1 1
-#define FUNC_2 2
-#define FUNC_3 3
-#define FUNC_4 4
-#define FUNC_5 5
-#define FUNC_6 6
-#define FUNC_7 7
-
-// SBDFO - Segment Bus Device Function Offset
-// 31:28 Segment (4-bits)
-// 27:20 Bus (8-bits)
-// 19:15 Device (5-bits)
-// 14:12 Function (3-bits)
-// 11:00 Offset (12-bits)
-
-#if 0
-#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
- (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
-#endif
-#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-/// CPUID data received registers format
-typedef struct _SB_CPUID_DATA {
- IN OUT unsigned int EAX_Reg; ///< CPUID instruction result in EAX
- IN OUT unsigned int EBX_Reg; ///< CPUID instruction result in EBX
- IN OUT unsigned int ECX_Reg; ///< CPUID instruction result in ECX
- IN OUT unsigned int EDX_Reg; ///< CPUID instruction result in EDX
-} SB_CPUID_DATA;
-
-#define WARM_RESET 1
-#define COLD_RESET 2 // Cold reset
-#define RESET_CPU 4 // Triggers a CPU reset
-
-/// HT frequency for external callbacks
-typedef enum {
- HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
- HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
- HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
- HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
- HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
- HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
- HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
- HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
- HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
- HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
- HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
- HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
- HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
- HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
- HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
- HT_FREQUENCY_3200M = 19 ///< HT speed 3200 for external callbacks
-} HT_FREQUENCIES;
-
-#ifndef BIT0
-#define BIT0 0x0000000000000001ull
-#endif
-#ifndef BIT1
-#define BIT1 0x0000000000000002ull
-#endif
-#ifndef BIT2
-#define BIT2 0x0000000000000004ull
-#endif
-#ifndef BIT3
-#define BIT3 0x0000000000000008ull
-#endif
-#ifndef BIT4
-#define BIT4 0x0000000000000010ull
-#endif
-#ifndef BIT5
-#define BIT5 0x0000000000000020ull
-#endif
-#ifndef BIT6
-#define BIT6 0x0000000000000040ull
-#endif
-#ifndef BIT7
-#define BIT7 0x0000000000000080ull
-#endif
-#ifndef BIT8
-#define BIT8 0x0000000000000100ull
-#endif
-#ifndef BIT9
-#define BIT9 0x0000000000000200ull
-#endif
-#ifndef BIT10
-#define BIT10 0x0000000000000400ull
-#endif
-#ifndef BIT11
-#define BIT11 0x0000000000000800ull
-#endif
-#ifndef BIT12
-#define BIT12 0x0000000000001000ull
-#endif
-#ifndef BIT13
-#define BIT13 0x0000000000002000ull
-#endif
-#ifndef BIT14
-#define BIT14 0x0000000000004000ull
-#endif
-#ifndef BIT15
-#define BIT15 0x0000000000008000ull
-#endif
-#ifndef BIT16
-#define BIT16 0x0000000000010000ull
-#endif
-#ifndef BIT17
-#define BIT17 0x0000000000020000ull
-#endif
-#ifndef BIT18
-#define BIT18 0x0000000000040000ull
-#endif
-#ifndef BIT19
-#define BIT19 0x0000000000080000ull
-#endif
-#ifndef BIT20
-#define BIT20 0x0000000000100000ull
-#endif
-#ifndef BIT21
-#define BIT21 0x0000000000200000ull
-#endif
-#ifndef BIT22
-#define BIT22 0x0000000000400000ull
-#endif
-#ifndef BIT23
-#define BIT23 0x0000000000800000ull
-#endif
-#ifndef BIT24
-#define BIT24 0x0000000001000000ull
-#endif
-#ifndef BIT25
-#define BIT25 0x0000000002000000ull
-#endif
-#ifndef BIT26
-#define BIT26 0x0000000004000000ull
-#endif
-#ifndef BIT27
-#define BIT27 0x0000000008000000ull
-#endif
-#ifndef BIT28
-#define BIT28 0x0000000010000000ull
-#endif
-#ifndef BIT29
-#define BIT29 0x0000000020000000ull
-#endif
-#ifndef BIT30
-#define BIT30 0x0000000040000000ull
-#endif
-#ifndef BIT31
-#define BIT31 0x0000000080000000ull
-#endif
-#ifndef BIT32
-#define BIT32 0x0000000100000000ull
-#endif
-#ifndef BIT33
-#define BIT33 0x0000000200000000ull
-#endif
-#ifndef BIT34
-#define BIT34 0x0000000400000000ull
-#endif
-#ifndef BIT35
-#define BIT35 0x0000000800000000ull
-#endif
-#ifndef BIT36
-#define BIT36 0x0000001000000000ull
-#endif
-#ifndef BIT37
-#define BIT37 0x0000002000000000ull
-#endif
-#ifndef BIT38
-#define BIT38 0x0000004000000000ull
-#endif
-#ifndef BIT39
-#define BIT39 0x0000008000000000ull
-#endif
-#ifndef BIT40
-#define BIT40 0x0000010000000000ull
-#endif
-#ifndef BIT41
-#define BIT41 0x0000020000000000ull
-#endif
-#ifndef BIT42
-#define BIT42 0x0000040000000000ull
-#endif
-#ifndef BIT43
-#define BIT43 0x0000080000000000ull
-#endif
-#ifndef BIT44
-#define BIT44 0x0000100000000000ull
-#endif
-#ifndef BIT45
-#define BIT45 0x0000200000000000ull
-#endif
-#ifndef BIT46
-#define BIT46 0x0000400000000000ull
-#endif
-#ifndef BIT47
-#define BIT47 0x0000800000000000ull
-#endif
-#ifndef BIT48
-#define BIT48 0x0001000000000000ull
-#endif
-#ifndef BIT49
-#define BIT49 0x0002000000000000ull
-#endif
-#ifndef BIT50
-#define BIT50 0x0004000000000000ull
-#endif
-#ifndef BIT51
-#define BIT51 0x0008000000000000ull
-#endif
-#ifndef BIT52
-#define BIT52 0x0010000000000000ull
-#endif
-#ifndef BIT53
-#define BIT53 0x0020000000000000ull
-#endif
-#ifndef BIT54
-#define BIT54 0x0040000000000000ull
-#endif
-#ifndef BIT55
-#define BIT55 0x0080000000000000ull
-#endif
-#ifndef BIT56
-#define BIT56 0x0100000000000000ull
-#endif
-#ifndef BIT57
-#define BIT57 0x0200000000000000ull
-#endif
-#ifndef BIT58
-#define BIT58 0x0400000000000000ull
-#endif
-#ifndef BIT59
-#define BIT59 0x0800000000000000ull
-#endif
-#ifndef BIT60
-#define BIT60 0x1000000000000000ull
-#endif
-#ifndef BIT61
-#define BIT61 0x2000000000000000ull
-#endif
-#ifndef BIT62
-#define BIT62 0x4000000000000000ull
-#endif
-#ifndef BIT63
-#define BIT63 0x8000000000000000ull
-#endif
-#endif
diff --git a/src/southbridge/amd/cimx/sb700/AmdSbLib.h b/src/southbridge/amd/cimx/sb700/AmdSbLib.h
deleted file mode 100644
index 8dd796821c..0000000000
--- a/src/southbridge/amd/cimx/sb700/AmdSbLib.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _AMD_SB_LIB_H_
-#define _AMD_SB_LIB_H_
-
-typedef signed char *va_list;
-#ifndef _INTSIZEOF
- #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
-#endif
-
-// Also support coding convention rules for var arg macros
-#ifndef va_start
- #define va_start(ap, v) ( ap = (va_list)&(v) + _INTSIZEOF (v) )
-#endif
-#define va_arg(ap, t) ( *(t *) ((ap += _INTSIZEOF (t)) - _INTSIZEOF (t)) )
-#define va_end(ap) ( ap = (va_list)0 )
-
-
-#pragma pack (push, 1)
-
-#define IMAGE_ALIGN 32*1024
-#define NUM_IMAGE_LOCATION 32
-
-//Entry Point Call
-typedef void (*CIM_IMAGE_ENTRY) (void* pConfig);
-
-//Hook Call
-
-typedef struct _CIMFILEHEADER
-{
- unsigned int AMDLogo;
- unsigned long long CreatorID;
- unsigned int Version1;
- unsigned int Version2;
- unsigned int Version3;
- unsigned int ModuleInfoOffset;
- unsigned int EntryPoint;
- unsigned int ImageBase;
- unsigned int RelocTableOffset;
- unsigned int ImageSize;
- unsigned short CheckSum;
- unsigned char ImageType;
- unsigned char Reserved2;
-} CIMFILEHEADER;
-
-#pragma pack (pop)
-
-typedef enum
-{
- AccWidthUint8 = 0,
- AccWidthUint16,
- AccWidthUint32,
-} ACC_WIDTH;
-
-#define S3_SAVE 0x80
-
-/**
- * AmdSbDispatcher - Dispatch Southbridge function
- *
- *
- *
- * @param[in] pConfig Southbridge configuration structure pointer.
- *
- */
-AGESA_STATUS AmdSbDispatcher (IN void *pConfig);
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb700/Kconfig b/src/southbridge/amd/cimx/sb700/Kconfig
deleted file mode 100644
index 045dd70679..0000000000
--- a/src/southbridge/amd/cimx/sb700/Kconfig
+++ /dev/null
@@ -1,66 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2012 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SOUTHBRIDGE_AMD_CIMX_SB700
- bool
- select IOAPIC
- select HAVE_USBDEBUG_OPTIONS
- select AMD_SB_CIMX
- select HAVE_HARD_RESET
-
-if SOUTHBRIDGE_AMD_CIMX_SB700
-config SATA_CONTROLLER_MODE
- hex
- default 0x0
- help
- 0x0 = Native IDE mode.
- 0x1 = RAID mode.
- 0x2 = AHCI mode.
- 0x3 = Legacy IDE mode.
- 0x4 = IDE->AHCI mode.
- 0x5 = AHCI mode as 7804 ID (AMD driver).
- 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
-
-config PCIB_ENABLE
- bool
- default n
- help
- n = Disable PCI Bridge Device 14 Function 4.
- y = Enable PCI Bridge Device 14 Function 4.
-
-config ACPI_SCI_IRQ
- hex
- default 0x9
- help
- Set SCI IRQ to 9.
-
-config EHCI_BAR
- hex
- default 0xfef00000
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
- string
- default "southbridge/amd/cimx/sb700/bootblock.c"
-
-config REDIRECT_SBCIMX_TRACE_TO_SERIAL
- bool "Redirect AMD Southbridge CIMX Trace to serial console"
- default n
- help
- This Option allows you to redirect the AMD Southbridge CIMX Trace
- debug information to the serial console.
-
- Warning: Only enable this option when debuging or tracing AMD CIMX code.
-
-endif #SOUTHBRIDGE_AMD_CIMX_SB700
diff --git a/src/southbridge/amd/cimx/sb700/Makefile.inc b/src/southbridge/amd/cimx/sb700/Makefile.inc
deleted file mode 100644
index 0b7614befe..0000000000
--- a/src/southbridge/amd/cimx/sb700/Makefile.inc
+++ /dev/null
@@ -1,34 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2012 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-
-# SB700 Platform Files
-
-romstage-y += early.c
-romstage-y += smbus.c smbus_spd.c
-romstage-y += reset.c
-romstage-y += ramtop.c
-
-postcar-y += ramtop.c
-
-ramstage-y += late.c
-ramstage-y += reset.c
-ramstage-y += ramtop.c
-
-ramstage-y += smbus.c
-ramstage-y += lpc.c
-
-romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb700/enable_usbdebug.c
-ramstage-$(CONFIG_USBDEBUG) += ../../sb700/enable_usbdebug.c
diff --git a/src/southbridge/amd/cimx/sb700/Platform.h b/src/southbridge/amd/cimx/sb700/Platform.h
deleted file mode 100644
index f83ec2375d..0000000000
--- a/src/southbridge/amd/cimx/sb700/Platform.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _AMD_SB_CIMx_PLATFORM_H_
-#define _AMD_SB_CIMx_PLATFORM_H_
-
-#pragma pack(push,1)
-
-#include "cbtypes.h"
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#ifdef NULL
-#undef NULL
-#endif
-#define NULL 0
-
-typedef struct _EXT_PCI_ADDR{
- UINT32 Reg :16;
- UINT32 Func:3;
- UINT32 Dev :5;
- UINT32 Bus :8;
-}EXT_PCI_ADDR;
-
-
-typedef union _PCI_ADDR{
- UINT32 ADDR;
- EXT_PCI_ADDR Addr;
-}PCI_ADDR;
-
-
-#ifdef CIM_DEBUG
-
-#if CIM_DEBUG & 2
-void TraceDebug( UINT32 Level, CHAR8 *Format, ...);
-#define TRACE(Arguments) TraceDebug Arguments
-#else
-#define TRACE(Arguments)
-#endif
-
-#if CIM_DEBUG & 1
-void TraceCode ( UINT32 Level, UINT32 Code);
-#define TRACECODE(Arguments) TraceCode Arguments
-#else
-#define TRACECODE(Arguments)
-#endif
-#else
- #ifdef TRACE
- #undef TRACE
- #endif
- #if IS_ENABLED(CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL)
- #define TRACE(Arguments) printk Arguments
- #else
- #define TRACE(Arguments) do {} while (0)
- #endif
- #define TRACECODE(Arguments)
-#endif
-
-#define FIXUP_PTR(ptr) ptr
-
-#pragma pack(pop)
-
-#include "OEM.h"
-#include "Amd.h"
-#include "ACPILIB.h"
-#include "SBTYPE.h"
-#include "sbAMDLIB.h"
-#include "SBCMNLIB.h"
-#include "SB700.h"
-#include "SBDEF.h"
-
-#define DMSG_SB_TRACE 0x02
-
-#endif /* _AMD_SB_CIMx_PLATFORM_H_ */
diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h
deleted file mode 100644
index 989e72905d..0000000000
--- a/src/southbridge/amd/cimx/sb700/amd_pci_int_defs.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMD_PCI_INT_DEFS_H
-#define AMD_PCI_INT_DEFS_H
-
-/*
- * PIRQ and device routing - these define the index
- * into the FCH PCI_INTR 0xC00/0xC01 interrupt
- * routing table
- */
-#define FCH_INT_TABLE_SIZE 0xD
-#define PIRQ_NC 0x1F /* Not Used */
-#define PIRQ_A 0x00 /* INT A */
-#define PIRQ_B 0x01 /* INT B */
-#define PIRQ_C 0x02 /* INT C */
-#define PIRQ_D 0x03 /* INT D */
-#define PIRQ_ACPI 0x04 /* ACPI */
-#define PIRQ_SMBUS 0x05 /* SMBUS */
-/* Index 6, 7, 8 are all reserved */
-#define PIRQ_E 0x09 /* INT E */
-#define PIRQ_F 0x0A /* INT F */
-#define PIRQ_G 0x0B /* INT G */
-#define PIRQ_H 0x0C /* INT H */
-
-#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h b/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h
deleted file mode 100644
index 3fdc339f49..0000000000
--- a/src/southbridge/amd/cimx/sb700/amd_pci_int_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMD_PCI_INT_TYPES_H
-#define AMD_PCI_INT_TYPES_H
-
-const char * intr_types[] = {
- [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t",
- [0x04] = "ACPI\t", "SMBUS\t", "RSVD\t", "RSVD\t", "RSVD\t",
- [0x09] = "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-};
-
-#endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/southbridge/amd/cimx/sb700/bootblock.c b/src/southbridge/amd/cimx/sb700/bootblock.c
deleted file mode 100644
index e10bb05ca9..0000000000
--- a/src/southbridge/amd/cimx/sb700/bootblock.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/io.h>
-
-static void sb700_enable_rom(void)
-{
- u32 word;
- u32 dword;
- pci_devfn_t dev;
-
- dev = PCI_DEV(0, 0x14, 0x03);
- /* SB700 LPC Bridge 0:20:3:44h.
- * BIT6: Port Enable for serial port 0x3f8-0x3ff
- * BIT29: Port Enable for KBC port 0x60 and 0x64
- * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
- */
- dword = pci_io_read_config32(dev, 0x44);
- //dword |= (1<<6) | (1<<29) | (1<<30);
- /*Turn on all of LPC IO Port decode enable */
- dword = 0xffffffff;
- pci_io_write_config32(dev, 0x44, dword);
-
- /* SB700 LPC Bridge 0:20:3:48h.
- * BIT0: Port Enable for SuperIO 0x2E-0x2F
- * BIT1: Port Enable for SuperIO 0x4E-0x4F
- * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
- * BIT6: Port Enable for RTC IO 0x70-0x73
- * BIT21: Port Enable for Port 0x80
- */
- dword = pci_io_read_config32(dev, 0x48);
- dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21);
- pci_io_write_config32(dev, 0x48, dword);
-
- /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
- /* Set the 4MB enable bits */
- word = pci_io_read_config16(dev, 0x6c);
- word = 0xFFC0;
- pci_io_write_config16(dev, 0x6c, word);
-}
-
-static void bootblock_southbridge_init(void)
-{
- /* Setup the ROM access for 2M */
- sb700_enable_rom();
-}
diff --git a/src/southbridge/amd/cimx/sb700/chip.h b/src/southbridge/amd/cimx/sb700/chip.h
deleted file mode 100644
index 488d2167fe..0000000000
--- a/src/southbridge/amd/cimx/sb700/chip.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CIMX_SB700_CHIP_H_
-#define _CIMX_SB700_CHIP_H_
-
-/*
- * configuration set in mainboard/devicetree.cb
- * boot_switch_sata_ide:
- * 0 -set SATA as primary, PATA(IDE) as secondary.
- * 1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
- * gpp_configuration - The configuration of General Purpose Port A/B/C/D
- * 0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
- * 2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
- * 3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
- * 4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
- */
-struct southbridge_amd_cimx_sb700_config
-{
- u32 boot_switch_sata_ide : 1;
- u8 gpp_configuration;
-};
-
-#endif /* _CIMX_SB700_CHIP_H_ */
diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c
deleted file mode 100644
index d706a56b30..0000000000
--- a/src/southbridge/amd/cimx/sb700/early.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include "Platform.h"
-#include "sb_cimx.h"
-#include "sb700_cfg.h" /*sb700_cimx_config*/
-#include <console/console.h>
-#include <commonlib/loglevel.h>
-#include "smbus.h"
-
-/**
- * @brief Get SouthBridge device number
- * @param[in] bus target bus number
- * @return southbridge device number
- */
-u32 get_sbdn(u32 bus)
-{
- pci_devfn_t dev;
-
- printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__);
- dev = pci_locate_device_on_bus(
- PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM),
- bus);
-
- printk(BIOS_SPEW, "SB700 - Early.c - %s - End.\n", __func__);
- return (dev >> 15) & 0x1f;
-}
-
-/**
- * @brief Enable A-Link Express Configuration DMA Access.
- */
-
-/**
- * @brief South Bridge CIMx romstage entry,
- * wrapper of sbPowerOnInit entry point.
- */
-void sb_Poweron_Init(void)
-{
- AMDSBCFG sb_early_cfg;
-
- printk(BIOS_SPEW, "cimx/sb700 early.c, %s() Start:\n", __func__);
- /* Enable A-Link Base Address */
- //sb_enable_alink ();
-
- sb700_cimx_config(&sb_early_cfg);
- sbPowerOnInit(&sb_early_cfg);
- printk(BIOS_SPEW, "cimx/sb700 early.c, %s() End\n", __func__);
-}
-
-void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base)
-{
- /* TODO: Now assume wio_index=0 */
- pci_devfn_t dev;
- u8 reg8;
-
- //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
- dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */
- pci_write_config32(dev, 0x64, base);
- reg8 = pci_read_config8(dev, 0x48);
- reg8 |= 1 << 2;
- pci_write_config8(dev, 0x48, reg8);
-}
-
-void sb7xx_51xx_disable_wideio(u8 wio_index)
-{
- /* TODO: Now assume wio_index=0 */
- pci_devfn_t dev;
- u8 reg8;
-
- //dev = pci_locate_device(PCI_ID(0x1002, 0x439d), 0); /* LPC Controller */
- dev = PCI_DEV(0, 0x14, 3); /* LPC Controller */
- pci_write_config32(dev, 0x64, 0);
- reg8 = pci_read_config8(dev, 0x48);
- reg8 &= ~(1 << 2);
- pci_write_config8(dev, 0x48, reg8);
-}
diff --git a/src/southbridge/amd/cimx/sb700/gpio_oem.h b/src/southbridge/amd/cimx/sb700/gpio_oem.h
deleted file mode 100644
index f28df0e474..0000000000
--- a/src/southbridge/amd/cimx/sb700/gpio_oem.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef _CIMX_SB_GPIO_OEM_H_
-#define _CIMX_SB_GPIO_OEM_H_
-
-/* Hudson-2 ACPI PmIO Space Define */
-#define SB_ACPI_BASE_ADDRESS 0x0400
-#define ACPI_MMIO_BASE 0xFED80000
-#define SB_CFG_BASE 0x000 // DWORD
-#define GPIO_BASE 0x100 // BYTE
-#define SMI_BASE 0x200 // DWORD
-#define PMIO_BASE 0x300 // DWORD
-#define PMIO2_BASE 0x400 // BYTE
-#define BIOS_RAM_BASE 0x500 // BYTE
-#define CMOS_RAM_BASE 0x600 // BYTE
-#define CMOS_BASE 0x700 // BYTE
-#define ASF_BASE 0x900 // DWORD
-#define SMBUS_BASE 0xA00 // DWORD
-#define WATCHDOG_BASE 0xB00 // ??
-#define HPET_BASE 0xC00 // DWORD
-#define IOMUX_BASE 0xD00 // BYTE
-#define MISC_BASE 0xE00
-#define SERIAL_DEBUG_BASE 0x1000
-#define GFX_DAC_BASE 0x1400
-#define CEC_BASE 0x1800
-#define XHCI_BASE 0x1C00
-#define ACPI_SMI_DATA_PORT 0xB1
-#define R_SB_ACPI_PM1_STATUS 0x00
-#define R_SB_ACPI_PM1_ENABLE 0x02
-#define R_SB_ACPI_PM_CONTROL 0x04
-#define R_SB_ACPI_EVENT_STATUS 0x20
-#define R_SB_ACPI_EVENT_ENABLE 0x24
-#define B_PWR_BTN_STATUS BIT8
-#define B_WAKEUP_STATUS BIT15
-#define B_SCI_EN BIT0
-#define SB_PM_INDEX_PORT 0xCD6
-#define SB_PM_DATA_PORT 0xCD7
-#define SB_PMIOA_REG24 0x24 // AcpiMmioEn
-#define MmioAddress( BaseAddr, Register ) \
- ( (UINTN)BaseAddr + \
- (UINTN)(Register) \
- )
-#define Mmio32Ptr( BaseAddr, Register ) \
- ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
-#define Mmio32( BaseAddr, Register ) \
- *Mmio32Ptr( BaseAddr, Register )
-
-
-#define SB_GPIO_REG01 1
-#define SB_GPIO_REG02 2
-#define SB_GPIO_REG15 15
-#define SB_GPIO_REG24 24
-#define SB_GPIO_REG25 25
-#define SB_GPIO_REG27 27
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
deleted file mode 100644
index 051b563a24..0000000000
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <device/device.h> /* device_t */
-#include <device/pci.h> /* device_operations */
-#include <device/pci_ids.h>
-#include <arch/ioapic.h>
-#include <device/smbus.h> /* smbus_bus_operations */
-#include <pc80/mc146818rtc.h>
-#include <pc80/i8254.h>
-#include <pc80/i8259.h>
-#include <console/console.h> /* printk */
-#include <device/pci_ehci.h>
-#include <arch/acpi.h>
-#include "lpc.h" /* lpc_read_resources */
-#include "Platform.h" /* Platform Specific Definitions */
-#include "sb_cimx.h"
-#include "sb700_cfg.h" /* sb700 Cimx configuration */
-#include "chip.h" /* struct southbridge_amd_cimx_sb700_config */
-
-static AMDSBCFG sb_late_cfg; //global, init in sb700_cimx_config
-static AMDSBCFG *sb_config = &sb_late_cfg;
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func Southbridge CIMx Function ID.
- * @param[in] data Southbridge Input Data.
- * @param[in] config Southbridge configuration structure pointer.
- *
- */
-u32 sb700_callout_entry(u32 func, u32 data, void* config)
-{
- u32 ret = 0;
-
- printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - Start.\n");
- printk(BIOS_DEBUG, "SB700 - Late.c - sb700_callout_entry - End.\n");
- return ret;
-}
-
-
-static struct pci_operations lops_pci = {
- .set_subsystem = pci_dev_set_subsystem,
-};
-
-static void lpc_enable_resources(device_t dev)
-{
-
- printk(BIOS_SPEW, "SB700 - Late.c - %s - Start.\n", __func__);
- pci_dev_enable_resources(dev);
- lpc_enable_childrens_resources(dev);
- printk(BIOS_SPEW, "SB700 - Late.c - %s - End.\n", __func__);
-}
-
-static void lpc_init(device_t dev)
-{
- printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
-
- cmos_check_update_date();
-
- /* Initialize the real time clock.
- * The 0 argument tells cmos_init not to
- * update CMOS unless it is invalid.
- * 1 tells cmos_init to always initialize the CMOS.
- */
- cmos_init(0);
-
- setup_i8259(); /* Initialize i8259 pic */
- setup_i8254(); /* Initialize i8254 timers */
-
- printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n");
-}
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
- /* Just a dummy */
- return current;
-}
-
-
-static struct device_operations lpc_ops = {
- .read_resources = lpc_read_resources,
- .set_resources = lpc_set_resources,
- .enable_resources = lpc_enable_resources,
-#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
- .write_acpi_tables = acpi_write_hpet,
-#endif
- .init = lpc_init,
- .scan_bus = scan_lpc_bus,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &lpc_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_LPC,
-};
-
-
-static struct device_operations sata_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver sata_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_SATA, //SATA IDE Mode 4390
-};
-
-static struct device_operations usb_ops = {
- .read_resources = pci_ehci_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
-};
-
-/*
- * The pci id of usb ctrl 0 and 1 are the same.
- */
-static const struct pci_driver usb_ohci123_driver __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
-};
-
-static const struct pci_driver usb_ohci3_driver __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_USB_18_1,
-};
-
-static const struct pci_driver usb_ehci123_driver __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
-};
-
-static const struct pci_driver usb_ohci4_driver __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_USB_20_5, /* OHCI-USB4 */
-};
-
-static struct device_operations azalia_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = 0,
- .scan_bus = 0,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver azalia_driver __pci_driver = {
- .ops = &azalia_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_HDA,
-};
-
-
-static struct device_operations pci_ops = {
- .read_resources = pci_bus_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_bus_enable_resources,
- .init = 0,
- .scan_bus = pci_scan_bridge,
- .reset_bus = pci_bus_reset,
- .ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
- .ops = &pci_ops,
- .vendor = PCI_VENDOR_ID_ATI,
- .device = PCI_DEVICE_ID_ATI_SB700_PCI,
-};
-
-
-static void sb700_enable(device_t dev)
-{
- struct southbridge_amd_cimx_sb700_config *sb_chip =
- (struct southbridge_amd_cimx_sb700_config *)(dev->chip_info);
-
- printk(BIOS_DEBUG, "sb700_enable() ");
- switch (dev->path.pci.devfn) {
- case (0x11 << 3) | 0: /* 0:11.0 SATA */
- sb700_cimx_config(sb_config);
- if (dev->enabled) {
- sb_config->SataController = CIMX_OPTION_ENABLED;
- if (1 == sb_chip->boot_switch_sata_ide)
- sb_config->SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
- else if (0 == sb_chip->boot_switch_sata_ide)
- sb_config->SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
- } else {
- sb_config->SataController = CIMX_OPTION_DISABLED;
- }
- break;
-
- case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */
- case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */
- case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */
- case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */
- break;
-
- case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
- {
- uintptr_t ioapic_base;
- printk(BIOS_DEBUG, "sm_init().\n");
- ioapic_base = IO_APIC_ADDR;
- clear_ioapic((void *)ioapic_base);
- /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
- if (CONFIG_MAX_CPUS >= 16)
- setup_ioapic((void *)ioapic_base, 0);
- else
- setup_ioapic((void *)ioapic_base, CONFIG_MAX_CPUS + 1);
- }
- break;
-
- case (0x14 << 3) | 1: /* 0:14:1 IDE */
- break;
-
- case (0x14 << 3) | 2: /* 0:14:2 HDA */
- if (dev->enabled) {
- if (AZALIA_DISABLE == sb_config->AzaliaController) {
- sb_config->AzaliaController = AZALIA_AUTO;
- }
- printk(BIOS_DEBUG, "hda enabled\n");
- } else {
- sb_config->AzaliaController = AZALIA_DISABLE;
- printk(BIOS_DEBUG, "hda disabled\n");
- }
- break;
-
-
- case (0x14 << 3) | 3: /* 0:14:3 LPC */
- break;
-
- case (0x14 << 3) | 4: /* 0:14:4 PCI */
- break;
-
- case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */
- /* call CIMX entry after last device enable */
- sb_Before_Pci_Init();
- break;
-
- default:
- break;
- }
-}
-
-struct chip_operations southbridge_amd_cimx_sb700_ops = {
- CHIP_NAME("ATI SB700")
- .enable_dev = sb700_enable,
-};
-
-/**
- * @brief SB Cimx entry point sbBeforePciInit wrapper
- */
-void sb_Before_Pci_Init(void)
-{
- printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
- /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
- //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
- //AmdSbDispatcher(sb_config);
- sbBeforePciInit(sb_config);
- printk(BIOS_SPEW, "sb700 %s End\n", __func__);
-}
-
-void sb_After_Pci_Init(void)
-{
- printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
- /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
- //sb_config->StdHeader.Func = SB_AFTER_PCI_INIT;
- //AmdSbDispatcher(sb_config);
- sbAfterPciInit(sb_config);
- printk(BIOS_SPEW, "sb700 %s End\n", __func__);
-}
-
-void sb_Late_Post(void)
-{
- printk(BIOS_SPEW, "sb700 %s Start\n", __func__);
- /* TODO: The sb700 cimx dispatcher not work yet, calling cimx API directly */
- //sb_config->StdHeader.Func = SB_LATE_POST_INIT;
- //AmdSbDispatcher(sb_config);
- sbLatePost(sb_config);
- printk(BIOS_SPEW, "sb700 %s End\n", __func__);
-}
diff --git a/src/southbridge/amd/cimx/sb700/lpc.c b/src/southbridge/amd/cimx/sb700/lpc.c
deleted file mode 100644
index 5a8faa85b6..0000000000
--- a/src/southbridge/amd/cimx/sb700/lpc.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci.h>
-#include "lpc.h"
-#include <arch/io.h>
-#include <arch/ioapic.h>
-#include <console/console.h> /* printk */
-#include <cbmem.h>
-
-void lpc_read_resources(device_t dev)
-{
- struct resource *res;
-
- printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
- /* Get the normal pci resources of this device */
- pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */
-
- /* Add an extra subtractive resource for both memory and I/O. */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- res->base = 0;
- res->size = 0x1000;
- res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
- res->base = 0xff800000;
- res->size = 0x00800000; /* 8 MB for flash */
- res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
- IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- /* Add a memory resource for the SPI BAR. */
- fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
-
- res = new_resource(dev, 3);
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- compact_resources(dev);
- printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
-}
-
-void lpc_set_resources(struct device *dev)
-{
- struct resource *res;
-
- printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
-
- /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
- res = find_resource(dev, 2);
- pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
-
- pci_dev_set_resources(dev);
-
- printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
-}
-
-/**
- * @brief Enable resources for children devices
- *
- * @param dev the device whose children's resources are to be enabled
- *
- */
-void lpc_enable_childrens_resources(device_t dev)
-{
- struct bus *link;
- u32 reg, reg_x;
- int var_num = 0;
- u16 reg_var[3];
-
- printk(BIOS_SPEW, "SB700 - Lpc.c - %s - Start.\n", __func__);
- reg = pci_read_config32(dev, 0x44);
- reg_x = pci_read_config32(dev, 0x48);
-
- for (link = dev->link_list; link; link = link->next) {
- device_t child;
- for (child = link->children; child;
- child = child->sibling) {
- if (child->enabled
- && (child->path.type == DEVICE_PATH_PNP)) {
- struct resource *res;
- for (res = child->resource_list; res; res = res->next) {
- u32 base, end; /* don't need long long */
- if (!(res->flags & IORESOURCE_IO))
- continue;
- base = res->base;
- end = resource_end(res);
-/*
- printk(BIOS_DEBUG, "sb700 lpc decode:%s, base=0x%08x, end=0x%08x\n",
- dev_path(child), base, end);
-*/
- switch (base) {
- case 0x60: /* KB */
- case 0x64: /* MS */
- reg |= (1 << 29);
- break;
- case 0x3f8: /* COM1 */
- reg |= (1 << 6);
- break;
- case 0x2f8: /* COM2 */
- reg |= (1 << 7);
- break;
- case 0x378: /* Parallel 1 */
- reg |= (1 << 0);
- break;
- case 0x3f0: /* FD0 */
- reg |= (1 << 26);
- break;
- case 0x220: /* Audio 0 */
- reg |= (1 << 8);
- break;
- case 0x300: /* Midi 0 */
- reg |= (1 << 18);
- break;
- case 0x400:
- reg_x |= (1 << 16);
- break;
- case 0x480:
- reg_x |= (1 << 17);
- break;
- case 0x500:
- reg_x |= (1 << 18);
- break;
- case 0x580:
- reg_x |= (1 << 19);
- break;
- case 0x4700:
- reg_x |= (1 << 22);
- break;
- case 0xfd60:
- reg_x |= (1 << 23);
- break;
- default:
- if (var_num >= 3)
- continue; /* only 3 var ; compact them ? */
- switch (var_num) {
- case 0:
- reg_x |= (1 << 2);
- break;
- case 1:
- reg_x |= (1 << 24);
- break;
- case 2:
- reg_x |= (1 << 25);
- break;
- }
- reg_var[var_num++] =
- base & 0xffff;
- }
- }
- }
- }
- }
- pci_write_config32(dev, 0x44, reg);
- pci_write_config32(dev, 0x48, reg_x);
- /* Set WideIO for as many IOs found (fall through is on purpose) */
- switch (var_num) {
- case 2:
- pci_write_config16(dev, 0x90, reg_var[2]);
- case 1:
- pci_write_config16(dev, 0x66, reg_var[1]);
- case 0:
- //pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
- break;
- }
- printk(BIOS_SPEW, "SB700 - Lpc.c - %s - End.\n", __func__);
-}
diff --git a/src/southbridge/amd/cimx/sb700/lpc.h b/src/southbridge/amd/cimx/sb700/lpc.h
deleted file mode 100644
index 6aea85e4da..0000000000
--- a/src/southbridge/amd/cimx/sb700/lpc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SB700_LPC_H_
-#define _SB700_LPC_H_
-
-
-#define SPIROM_BASE_ADDRESS_REGISTER 0xA0
-#define SPI_ROM_ENABLE 0x02
-#define SPI_BASE_ADDRESS 0xFEC10000
-
-void lpc_read_resources(device_t dev);
-void lpc_set_resources(device_t dev);
-void lpc_enable_childrens_resources(device_t dev);
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb700/ramtop.c b/src/southbridge/amd/cimx/sb700/ramtop.c
deleted file mode 100644
index cbc4596f57..0000000000
--- a/src/southbridge/amd/cimx/sb700/ramtop.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <cbmem.h>
-#include <southbridge/amd/cimx/cimx_util.h>
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
- u32 dword = ramtop;
- int nvram_pos = 0xfc, i;
- for (i = 0; i < 4; i++) {
- outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
- nvram_pos++;
- }
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
- u32 xdata = 0;
- int xnvram_pos = 0xfc, xi;
- for (xi = 0; xi < 4; xi++) {
- outb(xnvram_pos, BIOSRAM_INDEX);
- xdata &= ~(0xff << (xi * 8));
- xdata |= inb(BIOSRAM_DATA) << (xi *8);
- xnvram_pos++;
- }
- return xdata;
-}
diff --git a/src/southbridge/amd/cimx/sb700/reset.c b/src/southbridge/amd/cimx/sb700/reset.c
deleted file mode 100644
index 40e861c215..0000000000
--- a/src/southbridge/amd/cimx/sb700/reset.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <arch/io.h>
-#include <reset.h>
-
-#define HT_INIT_CONTROL 0x6C
-#define HTIC_BIOSR_Detect (1<<5)
-
-#define NODE_PCI(x, fn) (((CONFIG_CDB+x)<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
-
-static inline void set_bios_reset(void)
-{
- u32 nodes;
- u32 htic;
- pci_devfn_t dev;
- int i;
-
- nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
- for (i = 0; i < nodes; i++) {
- dev = NODE_PCI(i, 0);
- htic = pci_read_config32(dev, HT_INIT_CONTROL);
- htic &= ~HTIC_BIOSR_Detect;
- pci_write_config32(dev, HT_INIT_CONTROL, htic);
- }
-}
-
-void do_hard_reset(void)
-{
- set_bios_reset();
- /* Try rebooting through port 0xcf9 */
- /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
- outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
-}
-
-//SbReset();
-void do_soft_reset(void)
-{
- set_bios_reset();
- /* link reset */
- outb(0x06, 0x0cf9);
-}
diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h
deleted file mode 100644
index d64e07a5b3..0000000000
--- a/src/southbridge/amd/cimx/sb700/sb_cimx.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef _CIMX_H_
-#define _CIMX_H_
-
-#define PM_INDEX 0xcd6
-#define PM_DATA 0xcd7
-
-#define REV_SB700_A11 0x11
-#define REV_SB700_A12 0x12
-
-
-/**
- * AMD South Bridge CIMx entry point wrapper
- */
-void sb_Poweron_Init(void);
-void sb_Before_Pci_Init(void);
-void sb_After_Pci_Init(void);
-void sb_Late_Post(void);
-
-void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);
-void sb7xx_51xx_disable_wideio(u8 wio_index);
-
-/**
- * @brief Get SouthBridge device number, called by finalize_node_setup()
- * @param[in] bus target bus number
- * @return southbridge device number
- */
-u32 get_sbdn(u32 bus);
-#endif
diff --git a/src/southbridge/amd/cimx/sb700/smbus.c b/src/southbridge/amd/cimx/sb700/smbus.c
deleted file mode 100644
index 9d78cd06ee..0000000000
--- a/src/southbridge/amd/cimx/sb700/smbus.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/io.h>
-#include "smbus.h"
-#include <console/console.h> /* printk */
-
-static int smbus_wait_until_ready(u32 smbus_io_base)
-{
- u32 loops;
-
- loops = SMBUS_TIMEOUT;
- do {
- u8 val;
- val = inb(smbus_io_base + SMBHSTSTAT);
- val &= 0x1f;
- if (val == 0) { /* ready now */
- return 0;
- }
- outb(val, smbus_io_base + SMBHSTSTAT);
- } while (--loops);
-
- return -2; /* time out */
-}
-
-static int smbus_wait_until_done(u32 smbus_io_base)
-{
- u32 loops;
-
- loops = SMBUS_TIMEOUT;
- do {
- u8 val;
-
- val = inb(smbus_io_base + SMBHSTSTAT);
- val &= 0x1f; /* mask off reserved bits */
- if (val & 0x1c) {
- return -5; /* error */
- }
- if (val == 0x02) {
- outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */
- return 0;
- }
- } while (--loops);
-
- return -3; /* timeout */
-}
-
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; /* not ready */
- }
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - Start.\n");
- /* set the device I'm talking to */
- outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; /* Clear [4:2] */
- byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
- outb(byte, smbus_io_base + SMBHSTCTRL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; /* timeout or error */
- }
-
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTCMD);
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_recv_byte - End.\n");
- return byte;
-}
-
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; /* not ready */
- }
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - Start.\n");
- /* set the command... */
- outb(val, smbus_io_base + SMBHSTCMD);
-
- /* set the device I'm talking to */
- outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; /* Clear [4:2] */
- byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */
- outb(byte, smbus_io_base + SMBHSTCTRL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; /* timeout or error */
- }
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_send_byte - End.\n");
- return 0;
-}
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; /* not ready */
- }
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - Start.\n");
- /* set the command/address... */
- outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
- /* set the device I'm talking to */
- outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; /* Clear [4:2] */
- byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
- outb(byte, smbus_io_base + SMBHSTCTRL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; /* timeout or error */
- }
-
- /* read results of transaction */
- byte = inb(smbus_io_base + SMBHSTDAT0);
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_read_byte - End.\n");
- return byte;
-}
-
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
-{
- u8 byte;
-
- if (smbus_wait_until_ready(smbus_io_base) < 0) {
- return -2; /* not ready */
- }
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - Start.\n");
- /* set the command/address... */
- outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
- /* set the device I'm talking to */
- outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
- /* output value */
- outb(val, smbus_io_base + SMBHSTDAT0);
-
- byte = inb(smbus_io_base + SMBHSTCTRL);
- byte &= 0xe3; /* Clear [4:2] */
- byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */
- outb(byte, smbus_io_base + SMBHSTCTRL);
-
- /* poll for transaction completion */
- if (smbus_wait_until_done(smbus_io_base) < 0) {
- return -3; /* timeout or error */
- }
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - do_smbus_write_byte - End.\n");
- return 0;
-}
-
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
- u32 tmp;
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - Start.\n");
- outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
- tmp = inl(AB_DATA);
- /* rpr 4.2
- * For certain revisions of the chip, the ABCFG registers,
- * with an address of 0x100NN (where 'N' is any hexadecimal
- * number), require an extra programming step.*/
- outl(0, AB_INDX);
-
- tmp &= ~mask;
- tmp |= val;
-
- /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
- outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
- outl(tmp, AB_DATA);
- outl(0, AB_INDX);
- printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ab_indx - End.\n");
-}
-
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
-{
- u32 tmp;
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - Start.\n");
- outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
- tmp = inl(AB_DATA);
- /* rpr 4.2
- * For certain revisions of the chip, the ABCFG registers,
- * with an address of 0x100NN (where 'N' is any hexadecimal
- * number), require an extra programming step.*/
- outl(0, AB_INDX);
-
- tmp &= ~mask;
- tmp |= val;
-
- //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
- outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we don't have to do it again. */
- outl(tmp, AB_DATA);
- outl(0, AB_INDX);
- printk(BIOS_SPEW, "SB700 - Smbus.c - alink_rc_indx - End.\n");
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
-{
- u32 tmp;
-
- printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - Start.\n");
- /* read axindc to tmp */
- outl(space << 29 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(0, AB_INDX);
- outl(space << 29 | space << 3 | 0x34, AB_INDX);
- tmp = inl(AB_DATA);
- outl(0, AB_INDX);
-
- tmp &= ~mask;
- tmp |= val;
-
- /* write tmp */
- outl(space << 29 | space << 3 | 0x30, AB_INDX);
- outl(axindc, AB_DATA);
- outl(0, AB_INDX);
- outl(space << 29 | space << 3 | 0x34, AB_INDX);
- outl(tmp, AB_DATA);
- outl(0, AB_INDX);
- printk(BIOS_SPEW, "SB700 - Smbus.c - alink_ax_indx - End.\n");
-}
diff --git a/src/southbridge/amd/cimx/sb700/smbus.h b/src/southbridge/amd/cimx/sb700/smbus.h
deleted file mode 100644
index fa6ce9f609..0000000000
--- a/src/southbridge/amd/cimx/sb700/smbus.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SB700_SMBUS_H_
-#define _SB700_SMBUS_H_
-
-//#include <stdint.h>
-#include <Platform.h> /* SMBUS0_BASE_ADDRESS */
-#ifndef SMBUS0_BASE_ADDRESS
-#error SMBUS0_BASE_ADDRESS not define
-#endif
-#define SMBUS_IO_BASE SMBUS0_BASE_ADDRESS
-
-#define SMBHSTSTAT 0x0
-#define SMBSLVSTAT 0x1
-#define SMBHSTCTRL 0x2
-#define SMBHSTCMD 0x3
-#define SMBHSTADDR 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBHSTBLKDAT 0x7
-
-#define SMBSLVCTRL 0x8
-#define SMBSLVCMD_SHADOW 0x9
-#define SMBSLVEVT 0xa
-#define SMBSLVDAT 0xc
-
-/*//SB00.H
-#define AX_INDXC 0
-#define AX_INDXP 2
-#define AXCFG 4
-#define ABCFG 6
-#define RC_INDXC 1
-#define RC_INDXP 3
-*/
-
-#define AB_INDX 0xCD8
-#define AB_DATA (AB_INDX+4)
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100*1000*10)
-
-#define abcfg_reg(reg, mask, val) \
- alink_ab_indx((ABCFG), (reg), (mask), (val))
-#define axcfg_reg(reg, mask, val) \
- alink_ab_indx((AXCFG), (reg), (mask), (val))
-#define axindxc_reg(reg, mask, val) \
- alink_ax_indx((AX_INDXC), (reg), (mask), (val))
-#define axindxp_reg(reg, mask, val) \
- alink_ax_indx((AX_INDXP), (reg), (mask), (val))
-#define rcindxc_reg(reg, port, mask, val) \
- alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
-#define rcindxp_reg(reg, port, mask, val) \
- alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
-
-#endif //_SB700_SMBUS_H_
diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.c b/src/southbridge/amd/cimx/sb700/smbus_spd.c
deleted file mode 100644
index 73261c4ab4..0000000000
--- a/src/southbridge/amd/cimx/sb700/smbus_spd.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <device/pci_def.h>
-#include <device/device.h>
-#include <stdlib.h>
-#include "OEM.h" /* SMBUS0_BASE_ADDRESS */
-
-/* warning: Porting.h includes an open #pragma pack(1) */
-#include "Porting.h"
-#include "AGESA.h"
-#include "amdlib.h"
-#include "chip.h"
-#include "smbus_spd.h"
-
-#include <northbridge/amd/agesa/dimmSpd.h>
-
-/* uncomment for source level debug - GDB gets really confused otherwise. */
-//#pragma optimize ("", off)
-
-/**
- * Read a single SPD byte. If the first byte is being read, set up the
- * address and offset. Following bytes auto increment.
- */
-static UINT8 readSmbusByte(UINT16 iobase, UINT8 address, char *buffer,
- int offset, int initial_offset)
-{
- unsigned int status = -1;
- UINT64 time_limit;
-
- /* clear status register */
- __outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
- __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
-
- if (offset == initial_offset) {
- /* Set offset, set slave address and start reading */
- __outbyte(iobase + SMBUS_CONTROL_REG, offset);
- __outbyte(iobase + SMBUS_HOST_CMD_REG, address | READ_BIT);
- __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_BYTE_COMMAND);
- } else {
- /* Issue read command - auto increments to next byte */
- __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_READ_COMMAND);
- }
- /* time limit to avoid hanging for unexpected error status */
- time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
- while (__rdtsc() <= time_limit) {
- status = __inbyte(iobase + SMBUS_STATUS_REG);
- if ((status & SMBUS_INTERRUPT_MASK) == 0)
- continue; /* SMBusInterrupt not set, keep waiting */
- if ((status & HOSTBUSY_MASK) != 0)
- continue; /* HostBusy set, keep waiting */
- break;
- }
-
- if (status != STATUS__COMPLETED_SUCCESSFULLY)
- return AGESA_ERROR;
-
- buffer[0] = __inbyte(iobase + SMBUS_DATA0_REG);
- return AGESA_SUCCESS;
-}
-
-/**
- * Write a single smbus byte.
- */
-UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer,
- int offset)
-{
- unsigned int status = -1;
- UINT64 time_limit;
-
- /* clear status register */
- __outbyte(iobase + SMBUS_STATUS_REG, 0xFF);
- __outbyte(iobase + SMBUS_SLAVE_STATUS_REG, 0x1F);
-
- /* set offset, set slave address, set data and start writing */
- __outbyte(iobase + SMBUS_CONTROL_REG, offset);
- __outbyte(iobase + SMBUS_HOST_CMD_REG, address & (~READ_BIT));
- __outbyte(iobase + SMBUS_DATA0_REG, buffer);
- __outbyte(iobase + SMBUS_COMMAND_REG, SMBUS_WRITE_BYTE_COMMAND);
-
- /* time limit to avoid hanging for unexpected error status */
- time_limit = __rdtsc() + MAX_READ_TSC_COUNT;
- while (__rdtsc() <= time_limit) {
- status = __inbyte(iobase + SMBUS_STATUS_REG);
- if ((status & SMBUS_INTERRUPT_MASK) == 0)
- continue; /* SMBusInterrupt not set, keep waiting */
- if ((status & HOSTBUSY_MASK) != 0)
- continue; /* HostBusy set, keep waiting */
- break;
- }
-
- if (status != STATUS__COMPLETED_SUCCESSFULLY)
- return AGESA_ERROR;
-
- return AGESA_SUCCESS;
-}
-
-static void setupFch(UINT16 ioBase)
-{
- AMD_CONFIG_PARAMS StdHeader;
- UINT32 PciData32;
- UINT8 PciData8;
- PCI_ADDR PciAddress;
-
- /* Set SMBus MMIO. */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0x90);
- PciData32 = (ioBase & 0xFFFFFFF0) | BIT0;
- LibAmdPciWrite(AccessWidth32, PciAddress, &PciData32, &StdHeader);
-
- /* Enable SMBus MMIO. */
- PciAddress.AddressValue = MAKE_SBDFO (0, 0, 20, 0, 0xD2);
- LibAmdPciRead(AccessWidth8, PciAddress, &PciData8, &StdHeader);
- PciData8 |= BIT0;
- LibAmdPciWrite(AccessWidth8, PciAddress, &PciData8, &StdHeader);
-
- /* Set SMBus clock to 400 KHz */
- __outbyte(ioBase + SMBUS_CLOCK_REG, SMBUS_FREQUENCY_CONST / 400000);
-}
-
-/**
- * Read one or more SPD bytes from a DIMM.
- * Start with offset zero and read sequentially.
- * Reads 128 bytes in 7-8 ms at 400 KHz.
- */
-static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer,
- UINT16 count)
-{
- UINT16 index;
- UINT8 status;
- UINT8 initial_offset = 0;
-
- setupFch(iobase);
-
- for (index = initial_offset; index < count; index++) {
- status = readSmbusByte(iobase, SmbusSlaveAddress, &buffer[index], index,
- initial_offset);
- if (status != AGESA_SUCCESS)
- return status;
- }
-
- return status;
-}
-
-int smbus_readSpd(int spdAddress, char *buf, size_t len)
-{
- int ioBase = SMBUS0_BASE_ADDRESS;
- setupFch (ioBase);
- return readspd (ioBase, spdAddress, buf, len);
-}
diff --git a/src/southbridge/amd/cimx/sb700/smbus_spd.h b/src/southbridge/amd/cimx/sb700/smbus_spd.h
deleted file mode 100644
index e2f6c216b8..0000000000
--- a/src/southbridge/amd/cimx/sb700/smbus_spd.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SMBUS_SPD_H_
-#define _SMBUS_SPD_H_
-
-#define READ_BIT 0x01
-
-#define SMBUS_INTERRUPT_MASK 0x02
-#define HOSTBUSY_MASK 0x01
-
-#define SMBUS_READ_BYTE_COMMAND 0x48
-#define SMBUS_READ_COMMAND 0x44
-
-#define SMBUS_WRITE_BYTE_COMMAND 0x48
-
-#define MAX_READ_TSC_COUNT (2000000000 / 10)
-
-#define PMIO_INDEX_REG 0xCD6
-#define PMIO_DATA_REG 0xCD7
-
-#define SMBUS_BAR_LOW_BYTE 0x2C
-#define SMBUS_BAR_HIGH_BYTE 0x2D
-
-#define SMBUS_STATUS_REG 0x00
-#define SMBUS_SLAVE_STATUS_REG 0x01
-#define SMBUS_COMMAND_REG 0x02
-#define SMBUS_CONTROL_REG 0x03
-#define SMBUS_HOST_CMD_REG 0x04
-#define SMBUS_DATA0_REG 0x05
-#define SMBUS_CLOCK_REG 0x0E
-
-#define STATUS__COMPLETED_SUCCESSFULLY 0x02
-
-#define SMBUS_FREQUENCY_CONST 66000000 / 4
-
-/*
- * This function prototype is only used by the AMD Dinar mainboard. The SMBus
- * write is used to select which socket's SPD will be read by the subsequent
- * SPD read call. This function is being placed in the F15 wrapper code with
- * the other SPD read functions because the next step of the SPD read clean-up
- * will be to move the SMBus read/write functions into the southbridge to make
- * them more generic. Having the writeSmbusByte() function in the same file as
- * the readSmbusByte() function will ensure that the writeSmbusByte() function
- * is not overlooked.
- */
-UINT8 writeSmbusByte(UINT16 iobase, UINT8 address, UINT8 buffer, int offset);
-
-#endif
diff --git a/src/southbridge/amd/common/Makefile.inc b/src/southbridge/amd/common/Makefile.inc
index 107b2f66b4..92bb1493aa 100644
--- a/src/southbridge/amd/common/Makefile.inc
+++ b/src/southbridge/amd/common/Makefile.inc
@@ -1,4 +1,3 @@
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += amd_pci_util.c
ramstage-$(CONFIG_SOUTHBRIDGE_AMD_AGESA_BOLTON) += amd_pci_util.c