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-rw-r--r--src/southbridge/amd/agesa/hudson/lpc.c8
-rw-r--r--src/southbridge/amd/amd8111/lpc.c2
-rw-r--r--src/southbridge/amd/cimx/sb700/late.c8
-rw-r--r--src/southbridge/amd/cimx/sb800/late.c8
-rw-r--r--src/southbridge/amd/cimx/sb900/late.c8
-rw-r--r--src/southbridge/amd/cs5536/cs5536.c2
-rw-r--r--src/southbridge/amd/sb600/lpc.c2
-rw-r--r--src/southbridge/amd/sb600/sm.c2
-rw-r--r--src/southbridge/amd/sb700/lpc.c2
-rw-r--r--src/southbridge/amd/sb700/sm.c2
-rw-r--r--src/southbridge/amd/sb800/lpc.c2
-rw-r--r--src/southbridge/amd/sb800/sm.c2
12 files changed, 24 insertions, 24 deletions
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 20212ef223..1f60bc4ed9 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -70,14 +70,14 @@ static void lpc_init(device_t dev)
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
}
static void hudson_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c
index 8cabcab842..718b40bf9d 100644
--- a/src/southbridge/amd/amd8111/lpc.c
+++ b/src/southbridge/amd/amd8111/lpc.c
@@ -77,7 +77,7 @@ static void lpc_init(struct device *dev)
}
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* Initialize isa dma */
isa_dma_init();
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 42330ca1e9..20da0733f0 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -80,14 +80,14 @@ static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index b132bf17d0..7d6e221a6f 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -132,14 +132,14 @@ static void lpc_init(device_t dev)
{
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 7303bdceba..8d9b486831 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -102,14 +102,14 @@ static void lpc_init(device_t dev)
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
/* SB Configure HPET base and enable bit */
//- hpetInit(sb_config, &(sb_config->BuildParameters));
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
/* Initialize the real time clock.
- * The 0 argument tells rtc_init not to
+ * The 0 argument tells cmos_init not to
* update CMOS unless it is invalid.
- * 1 tells rtc_init to always initialize the CMOS.
+ * 1 tells cmos_init to always initialize the CMOS.
*/
- rtc_init(0);
+ cmos_init(0);
setup_i8259(); /* Initialize i8259 pic */
setup_i8254(); /* Initialize i8254 timers */
diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c
index e305594b7f..1f7eab87ad 100644
--- a/src/southbridge/amd/cs5536/cs5536.c
+++ b/src/southbridge/amd/cs5536/cs5536.c
@@ -245,7 +245,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb)
msr.lo = RTC_MONA;
wrmsr(MDD_RTC_MONA_IND, msr);
- rtc_init(0);
+ cmos_init(0);
isa_dma_init();
}
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index 7f1ca2597a..d8e63b557c 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -63,7 +63,7 @@ static void lpc_init(device_t dev)
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb600_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb600/sm.c b/src/southbridge/amd/sb600/sm.c
index 8de39a6429..a8e72c28f7 100644
--- a/src/southbridge/amd/sb600/sm.c
+++ b/src/southbridge/amd/sb600/sm.c
@@ -169,7 +169,7 @@ static void sm_init(device_t dev)
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/*3.4 Enabling IDE/PCIB Prefetch for Performance Enhancement */
abcfg_reg(0x10060, 9 << 17, 9 << 17);
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 6995861a8d..173de8369f 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -90,7 +90,7 @@ static void lpc_init(device_t dev)
}
#endif
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
void backup_top_of_ram(uint64_t ramtop)
diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c
index 0fb6556f37..8bb5378ff7 100644
--- a/src/southbridge/amd/sb700/sm.c
+++ b/src/southbridge/amd/sb700/sm.c
@@ -197,7 +197,7 @@ static void sm_init(device_t dev)
/* ab index */
pci_write_config32(dev, 0xF0, AB_INDX);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
/* 4.3 Enabling Upstream DMA Access */
axcfg_reg(0x04, 1 << 2, 1 << 2);
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index 12fd96fbfa..7a4dd831da 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -67,7 +67,7 @@ static void lpc_init(device_t dev)
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date(RTC_HAS_ALTCENTURY);
}
static void sb800_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index 315bc20b72..acdfb090a6 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -111,7 +111,7 @@ static void sm_init(device_t dev)
pm_iowrite(0xE2, (AB_INDX >> 16) & 0xFF);
pm_iowrite(0xE3, (AB_INDX >> 24) & 0xFF);
/* Initialize the real time clock */
- rtc_init(0);
+ cmos_init(0);
byte = pm_ioread(0x8);
byte |= 1 << 2 | 1 << 4;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 13:09:31 +0000