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-rw-r--r--src/southbridge/amd/agesa/hudson/early_setup.c2
-rw-r--r--src/southbridge/amd/agesa/hudson/sm.c4
-rw-r--r--src/southbridge/amd/agesa/hudson/smbus.c2
-rw-r--r--src/southbridge/amd/amd8111/acpi.c8
-rw-r--r--src/southbridge/amd/amd8111/early_ctrl.c2
-rw-r--r--src/southbridge/amd/amd8132/bridge.c6
-rw-r--r--src/southbridge/amd/cimx/sb800/fan.c42
-rw-r--r--src/southbridge/amd/cimx/sb800/smbus.c2
-rw-r--r--src/southbridge/amd/cimx/sb900/smbus.c2
-rw-r--r--src/southbridge/amd/pi/hudson/early_setup.c2
-rw-r--r--src/southbridge/amd/pi/hudson/smbus.c2
-rw-r--r--src/southbridge/amd/rs780/early_setup.c2
-rw-r--r--src/southbridge/amd/rs780/gfx.c2
-rw-r--r--src/southbridge/amd/sb700/early_setup.c2
-rw-r--r--src/southbridge/amd/sb700/ramtop.c2
-rw-r--r--src/southbridge/amd/sb700/sata.c6
-rw-r--r--src/southbridge/amd/sb800/early_setup.c2
-rw-r--r--src/southbridge/amd/sb800/sata.c8
-rw-r--r--src/southbridge/amd/sb800/sm.c4
-rw-r--r--src/southbridge/amd/sb800/smbus.c2
-rw-r--r--src/southbridge/amd/sr5650/pcie.c6
21 files changed, 55 insertions, 55 deletions
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index a5f46bec24..75da9dd91e 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -96,7 +96,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c
index 1b6f5ae99f..30fcd3772d 100644
--- a/src/southbridge/amd/agesa/hudson/sm.c
+++ b/src/southbridge/amd/agesa/hudson/sm.c
@@ -45,8 +45,8 @@
#define BIT6 (1 << 6)
#define BIT7 (1 << 7)
-#define BIT8 (1 << 8 )
-#define BIT9 (1 << 9 )
+#define BIT8 (1 << 8)
+#define BIT9 (1 << 9)
#define BIT10 (1 << 10)
#define BIT11 (1 << 11)
#define BIT12 (1 << 12)
diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c
index ce0361a121..33bc91774b 100644
--- a/src/southbridge/amd/agesa/hudson/smbus.c
+++ b/src/southbridge/amd/agesa/hudson/smbus.c
@@ -219,7 +219,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port,
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc,
u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/amd8111/acpi.c b/src/southbridge/amd/amd8111/acpi.c
index 0948683b31..da7a1d8086 100644
--- a/src/southbridge/amd/amd8111/acpi.c
+++ b/src/southbridge/amd/amd8111/acpi.c
@@ -168,17 +168,17 @@ static void acpi_init(struct device *dev)
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if (on) {
- pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
- outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
+ pm10_bar = (pci_read_config16(dev, 0x58) & 0xff00);
+ outl(((on << 1) + 0x10), (pm10_bar + 0x10));
inl(pm10_bar + 0x10);
on = 8-on;
printk(BIOS_DEBUG, "Throttling CPU %2d.%1.1d percent.\n",
- (on*12)+(on>>1),(on&1)*5);
+ (on * 12) + (on >> 1), (on & 1) * 5);
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
pm_base = pci_read_config16(dev, 0x58) & 0xff00;
- printk(BIOS_DEBUG, "pm_base: 0x%04x\n",pm_base);
+ printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base);
#endif
}
diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c
index aa323e45a0..d04646cf85 100644
--- a/src/southbridge/amd/amd8111/early_ctrl.c
+++ b/src/southbridge/amd/amd8111/early_ctrl.c
@@ -68,7 +68,7 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
pci_write_config8(dev, 0x74, 4);
- /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+ /* set VFSMAF (VID/FID System Management Action Field) to 2 */
pci_write_config32(dev, 0x70, 2<<12);
}
diff --git a/src/southbridge/amd/amd8132/bridge.c b/src/southbridge/amd/amd8132/bridge.c
index 52306ab697..162a36129b 100644
--- a/src/southbridge/amd/amd8132/bridge.c
+++ b/src/southbridge/amd/amd8132/bridge.c
@@ -213,7 +213,7 @@ static void amd8132_pcix_init(struct device *dev)
if (chip_rev == 0x01) {
/* Errata #37 */
byte = pci_read_config8(dev, 0x0c);
- if (byte == 0x08 )
+ if (byte == 0x08)
pci_write_config8(dev, 0x0c, 0x10);
#if 0
@@ -272,7 +272,7 @@ static void amd8132_pcix_init(struct device *dev)
/* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
dword = pci_read_config32(dev, 0xdc);
- dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE
+ dword |= (1<<1) | (1<<4); // stream disable 1 to 0, DBLINSRATE
dword |= (1<<18)|(1<<26);
dword &= ~((3<<16)|(3<<24));
pci_write_config32(dev, 0xdc, dword);
@@ -385,7 +385,7 @@ static void amd8132_ioapic_init(struct device *dev)
}
- if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+ if ((chip_rev == 0x11) || (chip_rev == 0x12)) {
//for b1 b2
/* Errata #73 */
dword = pci_read_config32(dev, 0x80);
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index 977ffb6f62..db87b6ac87 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -70,7 +70,7 @@ void init_sb800_IMC_fans(struct device *dev)
*
* Device 20, Function 3, Reg 0xA4
* [0]: if 1, the address specified in IMC_PortAddress is used.
- * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E )
+ * [15:1] IMC_PortAddress bits 15:1 (0x17 - address 0x2E)
*/
pci_write_config16(dev, 0xA4, sb_chip->imc_port_address | 0x01);
@@ -102,7 +102,7 @@ if (sb_chip->imc_fan_zone0_enabled) {
sb_config.Pecstruct.MSGFun81zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun81zone0MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_config_vals[i];
/* EC LDN9 function 83 zone 0 - Temperature Thresholds */
@@ -110,14 +110,14 @@ if (sb_chip->imc_fan_zone0_enabled) {
sb_config.Pecstruct.MSGFun83zone0MSGREG1 = IMC_ZONE0;
sb_config.Pecstruct.MSGFun83zone0MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone0MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_thresholds[i];
/*EC LDN9 function 85 zone 0 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone0MSGREG1 = IMC_ZONE0;
message_ptr = &sb_config.Pecstruct.MSGFun85zone0MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone0_fanspeeds[i];
}
@@ -133,7 +133,7 @@ if (sb_chip->imc_fan_zone1_enabled) {
sb_config.Pecstruct.MSGFun81zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun81zone1MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_config_vals[i];
/* EC LDN9 function 83 zone 1 - Temperature Thresholds */
@@ -141,14 +141,14 @@ if (sb_chip->imc_fan_zone1_enabled) {
sb_config.Pecstruct.MSGFun83zone1MSGREG1 = IMC_ZONE1;
sb_config.Pecstruct.MSGFun83zone1MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone1MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_thresholds[i];
/* EC LDN9 function 85 zone 1 - Fan Speeds */
sb_config.Pecstruct.MSGFun85zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone1MSGREG1 = IMC_ZONE1;
message_ptr = &sb_config.Pecstruct.MSGFun85zone1MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone1_fanspeeds[i];
}
@@ -165,7 +165,7 @@ if (sb_chip->imc_fan_zone2_enabled) {
sb_config.Pecstruct.MSGFun81zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun81zone2MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_config_vals[i];
/* EC LDN9 function 83 zone 2 */
@@ -173,14 +173,14 @@ if (sb_chip->imc_fan_zone2_enabled) {
sb_config.Pecstruct.MSGFun83zone2MSGREG1 = IMC_ZONE2;
sb_config.Pecstruct.MSGFun83zone2MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone2MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_thresholds[i];
/* EC LDN9 function 85 zone 2 */
sb_config.Pecstruct.MSGFun85zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone2MSGREG1 = IMC_ZONE2;
message_ptr = &sb_config.Pecstruct.MSGFun85zone2MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone2_fanspeeds[i];
}
@@ -197,7 +197,7 @@ if (sb_chip->imc_fan_zone3_enabled) {
sb_config.Pecstruct.MSGFun81zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun81zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun81zone3MSGREG2;
- for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_CONFIG_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_config_vals[i];
/* EC LDN9 function 83 zone 3 */
@@ -205,14 +205,14 @@ if (sb_chip->imc_fan_zone3_enabled) {
sb_config.Pecstruct.MSGFun83zone3MSGREG1 = IMC_ZONE3;
sb_config.Pecstruct.MSGFun83zone3MSGREGB = 0x00;
message_ptr = &sb_config.Pecstruct.MSGFun83zone3MSGREG2;
- for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_THRESHOLD_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_thresholds[i];
/* EC LDN9 function 85 zone 3 */
sb_config.Pecstruct.MSGFun85zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun85zone3MSGREG1 = IMC_ZONE3;
message_ptr = &sb_config.Pecstruct.MSGFun85zone3MSGREG2;
- for (i = 0; i < IMC_FAN_SPEED_COUNT; i++ )
+ for (i = 0; i < IMC_FAN_SPEED_COUNT; i++)
*(message_ptr + i) = sb_chip->imc_zone3_fanspeeds[i];
}
@@ -231,11 +231,11 @@ if (sb_chip->imc_tempin0_enabled) {
/* EC LDN9 function 89 TEMPIN channel 0 */
sb_config.Pecstruct.MSGFun89zone0MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone0MSGREG1 = 0x00;
- sb_config.Pecstruct.MSGFun89zone0MSGREG2 = ( sb_chip->imc_tempin0_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone0MSGREG2 = (sb_chip->imc_tempin0_at & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG3 = ((sb_chip->imc_tempin0_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG4 = ((sb_chip->imc_tempin0_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG5 = ((sb_chip->imc_tempin0_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone0MSGREG6 = ( sb_chip->imc_tempin0_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone0MSGREG6 = (sb_chip->imc_tempin0_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG7 = ((sb_chip->imc_tempin0_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG8 = ((sb_chip->imc_tempin0_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone0MSGREG9 = ((sb_chip->imc_tempin0_ct >> 24) & 0xff);
@@ -249,11 +249,11 @@ if (sb_chip->imc_tempin1_enabled) {
/* EC LDN9 function 89 TEMPIN channel 1 */
sb_config.Pecstruct.MSGFun89zone1MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone1MSGREG1 = 0x01;
- sb_config.Pecstruct.MSGFun89zone1MSGREG2 = ( sb_chip->imc_tempin1_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone1MSGREG2 = (sb_chip->imc_tempin1_at & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG3 = ((sb_chip->imc_tempin1_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG4 = ((sb_chip->imc_tempin1_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG5 = ((sb_chip->imc_tempin1_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone1MSGREG6 = ( sb_chip->imc_tempin1_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone1MSGREG6 = (sb_chip->imc_tempin1_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG7 = ((sb_chip->imc_tempin1_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG8 = ((sb_chip->imc_tempin1_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone1MSGREG9 = ((sb_chip->imc_tempin1_ct >> 24) & 0xff);
@@ -267,11 +267,11 @@ if (sb_chip->imc_tempin2_enabled) {
/* EC LDN9 function 89 TEMPIN channel 2 */
sb_config.Pecstruct.MSGFun89zone2MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone2MSGREG1 = 0x02;
- sb_config.Pecstruct.MSGFun89zone2MSGREG2 = ( sb_chip->imc_tempin2_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone2MSGREG2 = (sb_chip->imc_tempin2_at & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG3 = ((sb_chip->imc_tempin2_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG4 = ((sb_chip->imc_tempin2_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG5 = ((sb_chip->imc_tempin2_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone2MSGREG6 = ( sb_chip->imc_tempin2_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone2MSGREG6 = (sb_chip->imc_tempin2_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG7 = ((sb_chip->imc_tempin2_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG8 = ((sb_chip->imc_tempin2_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone2MSGREG9 = ((sb_chip->imc_tempin2_ct >> 24) & 0xff);
@@ -285,11 +285,11 @@ if (sb_chip->imc_tempin3_enabled) {
/* EC LDN9 function 89 TEMPIN channel 3 */
sb_config.Pecstruct.MSGFun89zone3MSGREG0 = 0x00;
sb_config.Pecstruct.MSGFun89zone3MSGREG1 = 0x03;
- sb_config.Pecstruct.MSGFun89zone3MSGREG2 = ( sb_chip->imc_tempin3_at & 0xff);
+ sb_config.Pecstruct.MSGFun89zone3MSGREG2 = (sb_chip->imc_tempin3_at & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG3 = ((sb_chip->imc_tempin3_at >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG4 = ((sb_chip->imc_tempin3_at >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG5 = ((sb_chip->imc_tempin3_at >> 24) & 0xff);
- sb_config.Pecstruct.MSGFun89zone3MSGREG6 = ( sb_chip->imc_tempin3_ct & 0xff);
+ sb_config.Pecstruct.MSGFun89zone3MSGREG6 = (sb_chip->imc_tempin3_ct & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG7 = ((sb_chip->imc_tempin3_ct >> 8) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG8 = ((sb_chip->imc_tempin3_ct >> 16) & 0xff);
sb_config.Pecstruct.MSGFun89zone3MSGREG9 = ((sb_chip->imc_tempin3_ct >> 24) & 0xff);
diff --git a/src/southbridge/amd/cimx/sb800/smbus.c b/src/southbridge/amd/cimx/sb800/smbus.c
index 53b0a13977..a4426ff431 100644
--- a/src/southbridge/amd/cimx/sb800/smbus.c
+++ b/src/southbridge/amd/cimx/sb800/smbus.c
@@ -233,7 +233,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c
index aaa09686bc..389aa8e12d 100644
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
@@ -233,7 +233,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val)
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index b5a86dc959..47d20af04d 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -235,7 +235,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/pi/hudson/smbus.c b/src/southbridge/amd/pi/hudson/smbus.c
index ce0361a121..33bc91774b 100644
--- a/src/southbridge/amd/pi/hudson/smbus.c
+++ b/src/southbridge/amd/pi/hudson/smbus.c
@@ -219,7 +219,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port,
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc,
u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index 865b577279..017c76470a 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -35,7 +35,7 @@ static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
static void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index, u32 data)
{
- pci_write_config32(dev, index_reg, index /* | 0x80 */ );
+ pci_write_config32(dev, index_reg, index /* | 0x80 */);
pci_write_config32(dev, index_reg + 0x4, data);
}
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 43bfb02037..a765655ce7 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -247,7 +247,7 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
}
}
if (pMMIO[k].Limit != 0) {
- if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {
+ if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0) {
Base = 0;
}
else
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 6e072a6f82..a6569210f4 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -816,7 +816,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/sb700/ramtop.c b/src/southbridge/amd/sb700/ramtop.c
index d306fff6fd..4d261210fe 100644
--- a/src/southbridge/amd/sb700/ramtop.c
+++ b/src/southbridge/amd/sb700/ramtop.c
@@ -32,7 +32,7 @@ void backup_top_of_low_cacheable(uintptr_t ramtop)
int nvram_pos = 0xfc, i;
for (i = 0; i < 4; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
}
diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
index 1d1ac13890..975e5ac132 100644
--- a/src/southbridge/amd/sb700/sata.c
+++ b/src/southbridge/amd/sb700/sata.c
@@ -461,7 +461,7 @@ static void sata_init(struct device *dev)
else
printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master",
+ (i % 2) ? "Slave" : "Master",
(j == 10) ? "not " : "",
(j == 10) ? j : j + 1);
} else {
@@ -470,7 +470,7 @@ static void sata_init(struct device *dev)
else
printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master", i);
+ (i % 2) ? "Slave" : "Master", i);
}
}
@@ -510,7 +510,7 @@ static void sata_init(struct device *dev)
write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
- /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+ /* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */
/* word = 0x0000; */
/* word = pm_ioread(0x28); */
diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c
index d73b75d391..2ace9926c7 100644
--- a/src/southbridge/amd/sb800/early_setup.c
+++ b/src/southbridge/amd/sb800/early_setup.c
@@ -633,7 +633,7 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
for (i = 0; i < size; i++) {
outb(nvram_pos, BIOSRAM_INDEX);
- outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA);
+ outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
nvram_pos++;
}
diff --git a/src/southbridge/amd/sb800/sata.c b/src/southbridge/amd/sb800/sata.c
index 15b2527434..2186d37a41 100644
--- a/src/southbridge/amd/sb800/sata.c
+++ b/src/southbridge/amd/sb800/sata.c
@@ -177,7 +177,7 @@ static void sata_init(struct device *dev)
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
- if ( byte == 0x1 ) {
+ if (byte == 0x1) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");
@@ -212,13 +212,13 @@ static void sata_init(struct device *dev)
}
printk(BIOS_DEBUG, "%s %s device is %sready after %i tries\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master",
+ (i % 2) ? "Slave" : "Master",
(j == 10) ? "not " : "",
(j == 10) ? j : j + 1);
} else {
printk(BIOS_DEBUG, "No %s %s SATA drive on Slot%i\n",
(i / 2) ? "Secondary" : "Primary",
- (i % 2 ) ? "Slave" : "Master", i);
+ (i % 2) ? "Slave" : "Master", i);
}
}
@@ -237,7 +237,7 @@ static void sata_init(struct device *dev)
write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
/* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
- /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+ /* ????? why CIM does not set the AcpiGpe0BlkAddr, but use it??? */
/* word = 0x0000; */
/* word = pm_ioread(0x28); */
diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c
index d4ed3ccbe8..fdb6283fb0 100644
--- a/src/southbridge/amd/sb800/sm.c
+++ b/src/southbridge/amd/sb800/sm.c
@@ -45,8 +45,8 @@
#define BIT6 (1 << 6)
#define BIT7 (1 << 7)
-#define BIT8 (1 << 8 )
-#define BIT9 (1 << 9 )
+#define BIT8 (1 << 8)
+#define BIT9 (1 << 9)
#define BIT10 (1 << 10)
#define BIT11 (1 << 11)
#define BIT12 (1 << 12)
diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c
index 89244f4c4c..aa4133b92a 100644
--- a/src/southbridge/amd/sb800/smbus.c
+++ b/src/southbridge/amd/sb800/smbus.c
@@ -222,7 +222,7 @@ void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port,
/* space = 0: AX_INDXC, AX_DATAC
* space = 1: AX_INDXP, AX_DATAP
*/
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc,
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc,
u32 mask, u32 val)
{
u32 tmp;
diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 8986e676dc..159f3e43eb 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -665,7 +665,7 @@ void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
/* CIMx CommonPortInit settings that are not set above. */
pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */
- if ( port == 8 )
+ if (port == 8)
set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);
#if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished.
@@ -687,7 +687,7 @@ void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3);
/* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */
- if ( port != 8)
+ if (port != 8)
set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2);
/* Not sure about this PME setup */
@@ -806,7 +806,7 @@ void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);
/* Step 20: Disables immediate RCB timeout on link down */
- if (!((pci_read_config32(dev, 0x6C ) >> 6) & 0x01)) {
+ if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) {
set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-05 01:40:58 +0000