6 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/amd/rs690/rs690.c b/src/southbridge/amd/rs690/rs690.c
index e5d6a1e2e7..40913b3388 100644
--- a/src/southbridge/amd/rs690/rs690.c
+++ b/src/southbridge/amd/rs690/rs690.c
@@ -129,7 +129,7 @@ void rs690_enable(device_t dev)
 	device_t nb_dev = 0, sb_dev = 0;
 	int dev_ind;
 
-	printk_info("rs690_enable: dev=0x%x, VID_DID=0x%x\n", dev, get_vid_did(dev));
+	printk_info("rs690_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
 
 	nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
 	if (!nb_dev) {
diff --git a/src/southbridge/amd/rs690/rs690_gfx.c b/src/southbridge/amd/rs690/rs690_gfx.c
index d4c8755f8a..0ed5a81369 100644
--- a/src/southbridge/amd/rs690/rs690_gfx.c
+++ b/src/southbridge/amd/rs690/rs690_gfx.c
@@ -121,7 +121,7 @@ static void rs690_internal_gfx_enable(device_t dev)
 	device_t k8_f0 = 0, k8_f2 = 0;
 	device_t nb_dev = dev_find_slot(0, 0);
 
-	printk_info("rs690_internal_gfx_enable dev=0x%x, nb_dev=0x%x.\n", dev,
+	printk_info("rs690_internal_gfx_enable dev=0x%p, nb_dev=0x%p.\n", dev,
 		    nb_dev);
 
 	/* set APERTURE_SIZE, 128M. */
@@ -417,7 +417,7 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
 
-	printk_info("rs690_gfx_init, nb_dev=0x%x, dev=0x%x, port=0x%x.\n",
+	printk_info("rs690_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n",
 		    nb_dev, dev, port);
 
 	/* step 0, REFCLK_SEL, skip A11 revision */
diff --git a/src/southbridge/amd/rs690/rs690_pcie.c b/src/southbridge/amd/rs690/rs690_pcie.c
index 9691e4ed18..640fa75613 100644
--- a/src/southbridge/amd/rs690/rs690_pcie.c
+++ b/src/southbridge/amd/rs690/rs690_pcie.c
@@ -203,7 +203,7 @@ void rs690_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
 	device_t sb_dev;
 	struct southbridge_amd_rs690_config *cfg =
 	    (struct southbridge_amd_rs690_config *)nb_dev->chip_info;
-	printk_debug("gpp_sb_init nb_dev=0x%x, dev=0x%x, port=0x%x\n", nb_dev, dev, port);
+	printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
 
 	/* init GPP core */
 	set_pcie_enable_bits(nb_dev, 0x20 | PCIE_CORE_INDEX_GPPSB, 1 << 8,
diff --git a/src/southbridge/amd/sb600/sb600_hda.c b/src/southbridge/amd/sb600/sb600_hda.c
index 7286eb25b7..41b94a90de 100644
--- a/src/southbridge/amd/sb600/sb600_hda.c
+++ b/src/southbridge/amd/sb600/sb600_hda.c
@@ -302,7 +302,7 @@ static void hda_init(struct device *dev)
 		return;
 
 	base = (u8 *) ((u32)res->base);
-	printk_debug("base = %08x\n", base);
+	printk_debug("base = %p\n", base);
 	codec_mask = codec_detect(base);
 
 	if (codec_mask) {
diff --git a/src/southbridge/amd/sb600/sb600_sata.c b/src/southbridge/amd/sb600/sb600_sata.c
index 933f59936e..b285a6bc7a 100644
--- a/src/southbridge/amd/sb600/sb600_sata.c
+++ b/src/southbridge/amd/sb600/sb600_sata.c
@@ -96,7 +96,7 @@ static void sata_init(struct device *dev)
 	printk_spew("sata_bar2=%x\n", sata_bar2);	/* 3040 */
 	printk_spew("sata_bar3=%x\n", sata_bar3);	/* 3080 */
 	printk_spew("sata_bar4=%x\n", sata_bar4);	/* 3000 */
-	printk_spew("sata_bar5=%x\n", sata_bar5);	/* e0309000 */
+	printk_spew("sata_bar5=%p\n", sata_bar5);	/* e0309000 */
 
 	/* Program the 2C to 0x43801002 */
 	dword = 0x43801002;
diff --git a/src/southbridge/amd/sb600/sb600_usb.c b/src/southbridge/amd/sb600/sb600_usb.c
index 51759c969b..2002114f81 100644
--- a/src/southbridge/amd/sb600/sb600_usb.c
+++ b/src/southbridge/amd/sb600/sb600_usb.c
@@ -94,7 +94,7 @@ static void usb_init2(struct device *dev)
 	/* pci_write_config32(dev, 0xf8, dword); */
 
 	usb2_bar0 = (u8 *) (pci_read_config32(dev, 0x10) & ~0xFF);
-	printk_info("usb2_bar0=%x\n", usb2_bar0);
+	printk_info("usb2_bar0=%p\n", usb2_bar0);
 
 	/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */
 	dword = 0x00020F00;