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-rw-r--r--src/southbridge/amd/amd8111/Config.lb1
-rw-r--r--src/southbridge/amd/amd8111/amd8111_reset.c45
2 files changed, 46 insertions, 0 deletions
diff --git a/src/southbridge/amd/amd8111/Config.lb b/src/southbridge/amd/amd8111/Config.lb
index 5bbbaba65e..57d299cfbf 100644
--- a/src/southbridge/amd/amd8111/Config.lb
+++ b/src/southbridge/amd/amd8111/Config.lb
@@ -8,3 +8,4 @@ driver amd8111_usb2.o
driver amd8111_ac97.o
driver amd8111_nic.o
driver amd8111_pci.o
+object amd8111_reset.o
diff --git a/src/southbridge/amd/amd8111/amd8111_reset.c b/src/southbridge/amd/amd8111/amd8111_reset.c
new file mode 100644
index 0000000000..822a1e378f
--- /dev/null
+++ b/src/southbridge/amd/amd8111/amd8111_reset.c
@@ -0,0 +1,45 @@
+#include <arch/io.h>
+
+#define PCI_DEV(BUS, DEV, FN) ( \
+ (((BUS) & 0xFF) << 16) | \
+ (((DEV) & 0x1f) << 11) | \
+ (((FN) & 0x7) << 8))
+
+#define AMD8111_RESET PCI_DEV( \
+ HARD_RESET_BUS, \
+ HARD_RESET_DEVICE, \
+ HARD_RESET_FUNCTION)
+
+typedef unsigned device_t;
+
+static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
+{
+ unsigned addr;
+ addr = dev | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outb(value, 0xCFC + (addr & 3));
+}
+
+static void pci_write_config32(device_t dev, unsigned where, unsigned value)
+{
+ unsigned addr;
+ addr = dev | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ outl(value, 0xCFC);
+}
+
+static unsigned pci_read_config32(device_t dev, unsigned where)
+{
+ unsigned addr;
+ addr = dev | where;
+ outl(0x80000000 | (addr & ~3), 0xCF8);
+ return inl(0xCFC);
+}
+
+#include "../../../northbridge/amd/amdk8/reset_test.c"
+
+void hard_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(AMD8111_RESET, 0x47, 1);
+}