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-rw-r--r--src/southbridge/amd/agesa/hudson/lpc.c2
-rw-r--r--src/southbridge/amd/agesa/hudson/sd.c2
-rw-r--r--src/southbridge/amd/agesa/hudson/spi.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 132a3335af..8d07e6487e 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -38,7 +38,7 @@ static void lpc_init(struct device *dev)
struct device *sm_dev;
/* Enable the LPC Controller */
- sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
+ sm_dev = pcidev_on_root(0x14, 0);
dword = pci_read_config32(sm_dev, 0x64);
dword |= 1 << 20;
pci_write_config32(sm_dev, 0x64, dword);
diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c
index e98be57575..878f136205 100644
--- a/src/southbridge/amd/agesa/hudson/sd.c
+++ b/src/southbridge/amd/agesa/hudson/sd.c
@@ -25,7 +25,7 @@ static void sd_init(struct device *dev)
{
u32 stepping;
- stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC);
+ stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC);
struct southbridge_amd_agesa_hudson_config *sd_chip =
(struct southbridge_amd_agesa_hudson_config *)(dev->chip_info);
diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c
index 94846514ce..ade7a02376 100644
--- a/src/southbridge/amd/agesa/hudson/spi.c
+++ b/src/southbridge/amd/agesa/hudson/spi.c
@@ -81,7 +81,7 @@ void spi_init(void)
{
struct device *dev;
- dev = dev_find_slot(0, PCI_DEVFN(0x14, 3));
+ dev = pcidev_on_root(0x14, 3);
spibar = pci_read_config32(dev, 0xA0) & ~0x1F;
}