diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/pci_irqs.asl | 144 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/acpi/southbridge.asl | 3 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.c | 17 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 208 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/irq.h | 89 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/include/soc/pci_devs.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/common/block/uart/uart.c | 24 |
8 files changed, 233 insertions, 254 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dfb1be4879..95e5440eeb 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -89,6 +89,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS diff --git a/src/soc/intel/cannonlake/acpi/pci_irqs.asl b/src/soc/intel/cannonlake/acpi/pci_irqs.asl deleted file mode 100644 index 17e3aa51c6..0000000000 --- a/src/soc/intel/cannonlake/acpi/pci_irqs.asl +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <soc/irq.h> - -Name (PICP, Package () { - /* PCI Bridge */ - /* cAVS, SMBus, GbE, Nothpeak */ - Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, - /* SerialIo and SCS */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* PCI Express Port 9-16 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* PCI Express Port 1-8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, -#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) - /* PCI Express Port 17-24 */ - Package(){0x001BFFFF, 0, 0, PCIE_17_IRQ }, - Package(){0x001BFFFF, 1, 0, PCIE_18_IRQ }, - Package(){0x001BFFFF, 2, 0, PCIE_19_IRQ }, - Package(){0x001BFFFF, 3, 0, PCIE_20_IRQ }, -#endif - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, - /* SerialIo */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* SATA controller */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* CSME (HECI, IDE-R, Keyboard and Text redirection */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 2, 0, IDER_IRQ }, - Package(){0x0016FFFF, 3, 0, KT_IRQ }, - /* SerialIo */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, - Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, - Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - /* Integrated Sensor Hub */ - Package(){0x0013FFFF, 0, 0, ISH_IRQ }, - /* Thermal */ - Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, - /* Host Bridge */ - /* Root Port D1F0 */ - Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, - Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ }, - Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ }, - Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ }, - /* SA IGFX Device */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, - /* SA Thermal Device */ - Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ }, - /* SA IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* SA GNA Device */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, -}) - -Name (PICN, Package () { - /* - * If the setting change in pch_pirq_init(), then - * please make the same static IRQ changes here as well. - */ - /* D31: cAVS, SMBus, GbE, Nothpeak */ - Package () { 0x001FFFFF, 0, 0, 11 }, - Package () { 0x001FFFFF, 1, 0, 10 }, - Package () { 0x001FFFFF, 2, 0, 11 }, - Package () { 0x001FFFFF, 3, 0, 11 }, - /* D30: Can't use PIC*/ - /* D29: PCI Express Port 9-16 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: PCI Express Port 1-8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, -#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) - /* D27: PCI Express Port 17-24 */ - Package () { 0x001BFFFF, 0, 0, 11 }, - Package () { 0x001BFFFF, 1, 0, 10 }, - Package () { 0x001BFFFF, 2, 0, 11 }, - Package () { 0x001BFFFF, 3, 0, 11 }, -#endif - /* D25: Can't use PIC*/ - /* D23 */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME (HECI, IDE-R, KT redirection */ - Package () { 0x0016FFFF, 0, 0, 11 }, - Package () { 0x0016FFFF, 1, 0, 10 }, - Package () { 0x0016FFFF, 2, 0, 11 }, - Package () { 0x0016FFFF, 3, 0, 11 }, - /* D21: Can't use PIC*/ - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package () { 0x0014FFFF, 0, 0, 11 }, - Package () { 0x0014FFFF, 1, 0, 10 }, - Package () { 0x0014FFFF, 2, 0, 11 }, - Package () { 0x0014FFFF, 3, 0, 11 }, - /* D19: Can't use PIC*/ - /* Thermal */ - Package () { 0x0012FFFF, 0, 0, 11 }, - /* P.E.G. Root Port D1F0 */ - Package () { 0x0001FFFF, 0, 0, 11 }, - Package () { 0x0001FFFF, 1, 0, 10 }, - Package () { 0x0001FFFF, 2, 0, 11 }, - Package () { 0x0001FFFF, 3, 0, 11 }, - /* SA IGFX Device */ - Package () { 0x0002FFFF, 0, 0, 11 }, - /* SA Thermal Device */ - Package () { 0x0004FFFF, 0, 0, 11 }, - /* SA IPU Device */ - Package () { 0x0005FFFF, 0, 0, 11 }, - /* SA GNA Device */ - Package () { 0x0008FFFF, 0, 0, 11 }, -}) - -Method (_PRT) -{ - If (PICM) { - Return (^PICP) - } Else { - Return (^PICN) - } -} diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl index 01c22508c2..fa75673e45 100644 --- a/src/soc/intel/cannonlake/acpi/southbridge.asl +++ b/src/soc/intel/cannonlake/acpi/southbridge.asl @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* PCI IRQ assignment */ -#include "pci_irqs.asl" - /* PCR access */ #include <soc/intel/common/acpi/pcr.asl> diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index c651c59826..aa6fb1b357 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> +#include <intelblocks/irq.h> #include <intelblocks/itss.h> #include <intelblocks/pcie_rp.h> #include <intelblocks/xdci.h> @@ -156,6 +157,19 @@ void soc_init_pre_device(void *chip_info) pcie_rp_update_devicetree(pch_lp_rp_groups); } +static void cpu_fill_ssdt(const struct device *dev) +{ + generate_cpu_entries(dev); + + if (!generate_pin_irq_map()) + printk(BIOS_ERR, "ERROR: Failed to generate ACPI _PRT table!\n"); +} + +static void cpu_set_north_irqs(struct device *dev) +{ + irq_program_non_pch(); +} + static struct device_operations pci_domain_ops = { .read_resources = &pci_domain_read_resources, .set_resources = &pci_domain_set_resources, @@ -168,7 +182,8 @@ static struct device_operations pci_domain_ops = { static struct device_operations cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, - .acpi_fill_ssdt = generate_cpu_entries, + .enable_resources = cpu_set_north_irqs, + .acpi_fill_ssdt = cpu_fill_ssdt, }; static void soc_enable(struct device *dev) diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 89293442ba..c3989e50a6 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/util.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/power_limit.h> #include <intelblocks/pmclib.h> @@ -34,6 +35,163 @@ static const pci_devfn_t serial_io_dev[] = { PCH_DEVFN_UART2 }; +static const struct slot_irq_constraints irq_constraints[] = { + { + .slot = SA_DEV_SLOT_PEG, + .fns = { + FIXED_INT_PIRQ(SA_DEVFN_PEG0, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(SA_DEVFN_PEG1, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(SA_DEVFN_PEG2, PCI_INT_C, PIRQ_C), + }, + }, + { + .slot = SA_DEV_SLOT_IGD, + .fns = { + ANY_PIRQ(SA_DEVFN_IGD), + }, + }, + { + .slot = SA_DEV_SLOT_DSP, + .fns = { + ANY_PIRQ(SA_DEVFN_DSP), + }, + }, + { + .slot = SA_DEV_SLOT_IPU, + .fns = { + ANY_PIRQ(SA_DEVFN_IPU), + }, + }, + { + .slot = SA_DEV_SLOT_GNA, + .fns = { + ANY_PIRQ(SA_DEVFN_GNA), + }, + }, + { + .slot = PCH_DEV_SLOT_THERMAL, + .fns = { + ANY_PIRQ(PCH_DEVFN_THERMAL), + ANY_PIRQ(PCH_DEVFN_UFS), + DIRECT_IRQ(PCH_DEVFN_GSPI2), + }, + }, + { + .slot = PCH_DEV_SLOT_ISH, + .fns = { + DIRECT_IRQ(PCH_DEVFN_ISH), + }, + }, + { + .slot = PCH_DEV_SLOT_XHCI, + .fns = { + ANY_PIRQ(PCH_DEVFN_XHCI), + ANY_PIRQ(PCH_DEVFN_USBOTG), + ANY_PIRQ(PCH_DEVFN_CNViWIFI), + ANY_PIRQ(PCH_DEVFN_SDCARD), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO1, + .fns = { + DIRECT_IRQ(PCH_DEVFN_I2C0), + DIRECT_IRQ(PCH_DEVFN_I2C1), + DIRECT_IRQ(PCH_DEVFN_I2C2), + DIRECT_IRQ(PCH_DEVFN_I2C3), + }, + }, + { + .slot = PCH_DEV_SLOT_CSE, + .fns = { + ANY_PIRQ(PCH_DEVFN_CSE), + ANY_PIRQ(PCH_DEVFN_CSE_2), + ANY_PIRQ(PCH_DEVFN_CSE_IDER), + ANY_PIRQ(PCH_DEVFN_CSE_KT), + ANY_PIRQ(PCH_DEVFN_CSE_3), + ANY_PIRQ(PCH_DEVFN_CSE_4), + }, + }, + { + .slot = PCH_DEV_SLOT_SATA, + .fns = { + ANY_PIRQ(PCH_DEVFN_SATA), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO2, + .fns = { + DIRECT_IRQ(PCH_DEVFN_I2C4), + DIRECT_IRQ(PCH_DEVFN_I2C5), + DIRECT_IRQ(PCH_DEVFN_UART2), + }, + }, + { + .slot = PCH_DEV_SLOT_STORAGE, + .fns = { + ANY_PIRQ(PCH_DEVFN_EMMC), + }, + }, +#if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) + { + .slot = PCH_DEV_SLOT_PCIE_2, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE17, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE18, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE19, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE20, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE21, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE22, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE23, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE24, PCI_INT_D, PIRQ_D), + }, + }, +#endif + { + .slot = PCH_DEV_SLOT_PCIE, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCH_DEV_SLOT_PCIE_1, + .fns = { + FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE13, PCI_INT_A, PIRQ_A), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE14, PCI_INT_B, PIRQ_B), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE15, PCI_INT_C, PIRQ_C), + FIXED_INT_PIRQ(PCH_DEVFN_PCIE16, PCI_INT_D, PIRQ_D), + }, + }, + { + .slot = PCH_DEV_SLOT_SIO3, + .fns = { + DIRECT_IRQ(PCH_DEVFN_UART0), + DIRECT_IRQ(PCH_DEVFN_UART1), + DIRECT_IRQ(PCH_DEVFN_GSPI0), + DIRECT_IRQ(PCH_DEVFN_GSPI1), + }, + }, + { + .slot = PCH_DEV_SLOT_LPC, + .fns = { + ANY_PIRQ(PCH_DEVFN_HDA), + ANY_PIRQ(PCH_DEVFN_SMBUS), + ANY_PIRQ(PCH_DEVFN_GBE), + FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A) + }, + }, +}; + /* * Given an enum for PCH_SERIAL_IO_MODE, 1 needs to be subtracted to get the FSP * UPD expected value for Serial IO since valid enum index starts from 1. @@ -115,6 +273,46 @@ static void configure_gspi_cs(int idx, const config_t *config, } } +static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) +{ + const struct pci_irq_entry *entry = get_cached_pci_irqs(); + SI_PCH_DEVICE_INTERRUPT_CONFIG *config; + size_t pch_total = 0; + size_t cfg_count = 0; + + if (!entry) + return NULL; + + /* Count PCH devices */ + while (entry) { + if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) + ++pch_total; + entry = entry->next; + } + + /* Convert PCH device entries to FSP format */ + config = calloc(pch_total, sizeof(*config)); + entry = get_cached_pci_irqs(); + while (entry) { + if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { + entry = entry->next; + continue; + } + + config[cfg_count].Device = PCI_SLOT(entry->devfn); + config[cfg_count].Function = PCI_FUNC(entry->devfn); + config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; + config[cfg_count].Irq = entry->irq; + ++cfg_count; + + entry = entry->next; + } + + *out_count = cfg_count; + + return config; +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -527,6 +725,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SiSsidTablePtr = (uintptr_t)ssid_table; params->SiNumberOfSsidTableEntry = ARRAY_SIZE(ssid_table); + + /* Assign PCI IRQs */ + if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) + die("ERROR: Unable to assign PCI IRQs, and no ACPI _PRT table is defined\n"); + + size_t pch_count = 0; + const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); + params->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); + params->NumOfDevIntConfig = pch_count; + printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); } /* Mainboard GPIO Configuration */ diff --git a/src/soc/intel/cannonlake/include/soc/irq.h b/src/soc/intel/cannonlake/include/soc/irq.h index 1aa6036bcc..8d7b71f036 100644 --- a/src/soc/intel/cannonlake/include/soc/irq.h +++ b/src/soc/intel/cannonlake/include/soc/irq.h @@ -9,93 +9,4 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -#define SCI_IRQ9 9 -#define SCI_IRQ10 10 -#define SCI_IRQ11 11 -#define SCI_IRQ20 20 -#define SCI_IRQ21 21 -#define SCI_IRQ22 22 -#define SCI_IRQ23 23 - -#define TCO_IRQ9 9 -#define TCO_IRQ10 10 -#define TCO_IRQ11 11 -#define TCO_IRQ20 20 -#define TCO_IRQ21 21 -#define TCO_IRQ22 22 -#define TCO_IRQ23 23 - -#define LPSS_I2C0_IRQ 16 -#define LPSS_I2C1_IRQ 17 -#define LPSS_I2C2_IRQ 18 -#define LPSS_I2C3_IRQ 19 -#define LPSS_I2C4_IRQ 32 -#define LPSS_I2C5_IRQ 33 -#define LPSS_SPI0_IRQ 22 -#define LPSS_SPI1_IRQ 23 -#define LPSS_SPI2_IRQ 24 -#define LPSS_UART0_IRQ 20 -#define LPSS_UART1_IRQ 21 -#define LPSS_UART2_IRQ 34 -#define SDIO_IRQ 22 - -#define cAVS_INTA_IRQ 16 -#define SMBUS_INTA_IRQ 16 -#define SMBUS_INTB_IRQ 17 -#define GbE_INTA_IRQ 16 -#define GbE_INTC_IRQ 18 -#define TRACE_HUB_INTA_IRQ 16 -#define TRACE_HUB_INTD_IRQ 19 - -#define eMMC_IRQ 16 -#define SD_IRQ 19 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 -#define PCIE_14_IRQ 16 -#define PCIE_15_IRQ 17 -#define PCIE_16_IRQ 18 -#define PCIE_17_IRQ 19 -#define PCIE_18_IRQ 16 -#define PCIE_19_IRQ 17 -#define PCIE_20_IRQ 18 -#define PCIE_21_IRQ 19 - -#define SATA_IRQ 16 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define IDER_IRQ 18 -#define KT_IRQ 19 -#define HECI_3_IRQ 16 - -#define XHCI_IRQ 16 -#define OTG_IRQ 17 -#define PMC_SRAM_IRQ 18 -#define THERMAL_IRQ 16 -#define CNViWIFI_IRQ 19 -#define UFS_IRQ 16 -#define CIO_INTA_IRQ 16 -#define CIO_INTD_IRQ 19 -#define ISH_IRQ 20 - -#define PEG_RP_INTA_IRQ 16 -#define PEG_RP_INTB_IRQ 17 -#define PEG_RP_INTC_IRQ 18 -#define PEG_RP_INTD_IRQ 19 - -#define IGFX_IRQ 16 -#define SA_THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index a92b478a79..50ba6118e0 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -47,6 +47,7 @@ #define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) /* PCH Devices */ +#define MIN_PCH_SLOT PCH_DEV_SLOT_THERMAL #define PCH_DEV_SLOT_THERMAL 0x12 #define PCH_DEVFN_THERMAL _PCH_DEVFN(THERMAL, 0) #define PCH_DEVFN_UFS _PCH_DEVFN(THERMAL, 5) diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 8d96e44bfc..26edd47b66 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -9,11 +9,11 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include <intelblocks/irq.h> #include <intelblocks/lpss.h> #include <intelblocks/uart.h> #include <soc/pci_devs.h> #include <soc/iomap.h> -#include <soc/irq.h> #include <soc/nvs.h> #include "chip.h" @@ -203,23 +203,13 @@ static void uart_common_enable_resources(struct device *dev) static void uart_acpi_write_irq(const struct device *dev) { - struct acpi_irq irq; - - switch (dev->path.pci.devfn) { - case PCH_DEVFN_UART0: - irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART0_IRQ); - break; - case PCH_DEVFN_UART1: - irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART1_IRQ); - break; - case PCH_DEVFN_UART2: - irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART2_IRQ); - break; - default: - return; + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IRQ)) { + const int irq = get_pci_devfn_irq(dev->path.pci.devfn); + if (irq != INVALID_IRQ) { + struct acpi_irq airq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(irq); + acpi_device_write_interrupt(&airq); + } } - - acpi_device_write_interrupt(&irq); } /* |