diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/common/block/fast_spi/fast_spi.c | 18 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/fast_spi.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/skylake/smihandler.c | 34 |
3 files changed, 42 insertions, 19 deletions
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 078e0ae1f1..87cafb976e 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -274,3 +274,21 @@ void fast_spi_early_init(uintptr_t spi_base_address) /* Initialize SPI to allow BIOS to write/erase on flash. */ fast_spi_init(); } + +/* Read SPI Write Protect disable status. */ +bool fast_spi_wpd_status(void) +{ + return pci_read_config16(PCH_DEV_SPI, SPIBAR_BIOS_CONTROL) & + SPIBAR_BIOS_CONTROL_WPD; +} + +/* Enable SPI Write Protect. */ +void fast_spi_enable_wp(void) +{ + device_t dev = PCH_DEV_SPI; + uint8_t bios_cntl; + + bios_cntl = pci_read_config8(dev, SPIBAR_BIOS_CONTROL); + bios_cntl &= ~SPIBAR_BIOS_CONTROL_WPD; + pci_write_config8(dev, SPIBAR_BIOS_CONTROL, bios_cntl); +} diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 086143bc5f..6499ca5f5c 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -74,11 +74,18 @@ void fast_spi_cache_bios_region(void); * Caching. */ void fast_spi_early_init(uintptr_t spi_base_address); - /* * Fast SPI flash controller structure to allow SoCs to define bus-controller * mapping. */ extern const struct spi_ctrlr fast_spi_flash_ctrlr; +/* + * Read SPI Write protect disable bit. + */ +bool fast_spi_wpd_status(void); +/* + * Enable SPI Write protect. + */ +void fast_spi_enable_wp(void); #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index 3e79065cda..32764c644a 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -31,7 +31,6 @@ #include <pc80/mc146818rtc.h> #include <spi-generic.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pch.h> @@ -403,23 +402,22 @@ static void southbridge_smi_tco(void) return; if (tco_sts & (1 << 8)) { /* BIOSWR */ - u8 bios_cntl = pci_read_config16(PCH_DEV_SPI, BIOS_CNTL); - - if (bios_cntl & 1) { - /* - * BWE is RW, so the SMI was caused by a - * write to BWE, not by a write to the BIOS - * - * This is the place where we notice someone - * is trying to tinker with the BIOS. We are - * trying to be nice and just ignore it. A more - * resolute answer would be to power down the - * box. - */ - printk(BIOS_DEBUG, "Switching back to RO\n"); - pci_write_config32(PCH_DEV_SPI, BIOS_CNTL, - (bios_cntl & ~1)); - } /* No else for now? */ + if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) { + if (fast_spi_wpd_status()) { + /* + * BWE is RW, so the SMI was caused by a + * write to BWE, not by a write to the BIOS + * + * This is the place where we notice someone + * is trying to tinker with the BIOS. We are + * trying to be nice and just ignore it. A more + * resolute answer would be to power down the + * box. + */ + printk(BIOS_DEBUG, "Switching back to RO\n"); + fast_spi_enable_wp(); + } /* No else for now? */ + } } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); |