3 files changed, 24 insertions, 23 deletions

diff --git a/src/soc/intel/tigerlake/gpio.c b/src/soc/intel/tigerlake/gpio.c
index 4a5880b824..18b90702c1 100644
--- a/src/soc/intel/tigerlake/gpio.c
+++ b/src/soc/intel/tigerlake/gpio.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corp.
+ * Copyright (C) 2020 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -194,18 +194,18 @@ const struct pad_community *soc_gpio_get_community(size_t *num_communities)
 const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
 {
 	static const struct pmc_to_gpio_route routes[] = {
-		{ PMC_GPP_G, GPP_G },
 		{ PMC_GPP_B, GPP_B },
+		{ PMC_GPP_T, GPP_T },
 		{ PMC_GPP_A, GPP_A },
+		{ PMC_GPP_R, GPP_R },
+		{ PMC_GPD, GPD },
+		{ PMC_GPP_S, GPP_S },
 		{ PMC_GPP_H, GPP_H },
 		{ PMC_GPP_D, GPP_D },
+		{ PMC_GPP_U, GPP_U },
 		{ PMC_GPP_F, GPP_F },
-		{ PMC_GPD, GPD },
 		{ PMC_GPP_C, GPP_C },
 		{ PMC_GPP_E, GPP_E },
-		{ PMC_GPP_R, GPP_R },
-		{ PMC_GPP_S, GPP_S }
-
 	};
 	*num = ARRAY_SIZE(routes);
 	return routes;
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
index f0f2b11979..738e217cfd 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,18 +21,18 @@
  * The GPIO groups are accessed through register blocks called
  * communities.
  */
-#define GPP_G			0x0
-#define GPP_B			0x1
+#define GPP_B			0x0
+#define GPP_T			0x1
 #define GPP_A			0x2
 #define GPP_R			0x3
-#define GPP_S			0x4
-#define GPD			0x5
+#define GPD			0x4
+#define GPP_S			0x5
 #define GPP_H			0x6
 #define GPP_D			0x7
-#define GPP_F			0x8
-#define GPP_VGPIO		0x9
-#define GPP_C			0xA
-#define GPP_E			0xB
+#define GPP_U			0x8
+#define GPP_F			0xA
+#define GPP_C			0xB
+#define GPP_E			0xC
 
 #define GPIO_NUM_GROUPS		11
 #define GPIO_MAX_NUM_PER_GROUP	24
diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h
index bae04ab352..513eeb90e6 100644
--- a/src/soc/intel/tigerlake/include/soc/pmc.h
+++ b/src/soc/intel/tigerlake/include/soc/pmc.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2018 Intel Corporation.
+ * Copyright (C) 2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -115,17 +115,18 @@
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))
 
-#define  PMC_GPP_G			0x0
-#define  PMC_GPP_B			0x1
+#define  PMC_GPP_B			0x0
+#define  PMC_GPP_T			0x1
 #define  PMC_GPP_A			0x2
 #define  PMC_GPP_R			0x3
-#define  PMC_GPP_S			0x4
-#define  PMC_GPD			0x5
+#define  PMC_GPD			0x4
+#define  PMC_GPP_S			0x5
 #define  PMC_GPP_H			0x6
 #define  PMC_GPP_D			0x7
-#define  PMC_GPP_F			0x8
-#define  PMC_GPP_C			0xA
-#define  PMC_GPP_E			0xB
+#define  PMC_GPP_U			0x8
+#define  PMC_GPP_F			0xA
+#define  PMC_GPP_C			0xB
+#define  PMC_GPP_E			0xC
 
 #define GBLRST_CAUSE0			0x1924
 #define   GBLRST_CAUSE0_THERMTRIP	(1 << 5)