aboutsummaryrefslogtreecommitdiff
path: root/src/soc
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc')
-rw-r--r--src/soc/amd/cezanne/include/soc/iomap.h5
-rw-r--r--src/soc/amd/picasso/include/soc/iomap.h5
-rw-r--r--src/soc/amd/sabrina/include/soc/iomap.h5
-rw-r--r--src/soc/amd/stoneyridge/include/soc/iomap.h5
-rw-r--r--src/soc/intel/baytrail/acpi/lpc.asl4
-rw-r--r--src/soc/intel/braswell/acpi/lpc.asl4
-rw-r--r--src/soc/intel/broadwell/pch/acpi/lpc.asl10
7 files changed, 12 insertions, 26 deletions
diff --git a/src/soc/amd/cezanne/include/soc/iomap.h b/src/soc/amd/cezanne/include/soc/iomap.h
index a6efce72b5..fc04b256a8 100644
--- a/src/soc/amd/cezanne/include/soc/iomap.h
+++ b/src/soc/amd/cezanne/include/soc/iomap.h
@@ -15,11 +15,6 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h
index 1ce581ec3f..853008bcbc 100644
--- a/src/soc/amd/picasso/include/soc/iomap.h
+++ b/src/soc/amd/picasso/include/soc/iomap.h
@@ -10,11 +10,6 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000
#define AL2AHB_CONTROL_CLK_OFFSET 0x10
diff --git a/src/soc/amd/sabrina/include/soc/iomap.h b/src/soc/amd/sabrina/include/soc/iomap.h
index cfe4184888..7f9746b97f 100644
--- a/src/soc/amd/sabrina/include/soc/iomap.h
+++ b/src/soc/amd/sabrina/include/soc/iomap.h
@@ -15,11 +15,6 @@
#define GNB_IO_APIC_ADDR 0xfec01000
#define SPI_BASE_ADDRESS 0xfec10000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
/* FCH AL2AHB Registers */
#define ALINK_AHB_ADDRESS 0xfedc0000
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h
index 75c09734d8..76e6e778e2 100644
--- a/src/soc/amd/stoneyridge/include/soc/iomap.h
+++ b/src/soc/amd/stoneyridge/include/soc/iomap.h
@@ -16,11 +16,6 @@
#define APU_I2C2_BASE 0xfedc4000
#define APU_I2C3_BASE 0xfedc5000
-#include <arch/hpet.h> /* This will be removed in a follow-up patch */
-#if CONFIG_HPET_ADDRESS != HPET_BASE_ADDRESS
-#error HPET address must be 0xfed00000
-#endif
-
#define APU_UART0_BASE 0xfedc6000
#define APU_UART1_BASE 0xfedc8000
diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl
index c76cf22fb2..5933070a6b 100644
--- a/src/soc/intel/baytrail/acpi/lpc.asl
+++ b/src/soc/intel/baytrail/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
@@ -44,7 +46,7 @@ Device (LPCB)
Name(_CRS, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400)
})
}
diff --git a/src/soc/intel/braswell/acpi/lpc.asl b/src/soc/intel/braswell/acpi/lpc.asl
index 0a22162fc2..76af8fd20c 100644
--- a/src/soc/intel/braswell/acpi/lpc.asl
+++ b/src/soc/intel/braswell/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
/* Intel LPC Bus Device - 0:1f.0 */
Device (LPCB)
@@ -55,7 +57,7 @@ Device (LPCB)
Name(_CRS, ResourceTemplate()
{
- Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400)
+ Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, 0x400)
})
}
#endif
diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl
index e37c6d0682..b6b77c8ed2 100644
--- a/src/soc/intel/broadwell/pch/acpi/lpc.asl
+++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl
@@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <arch/hpet.h>
+
// Intel LPC Bus Device - 0:1f.0
Device (LPCB)
@@ -64,7 +66,7 @@ Device (LPCB)
Name (BUF0, ResourceTemplate ()
{
- Memory32Fixed (ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
+ Memory32Fixed (ReadOnly, HPET_BASE_ADDRESS, 0x400, FED0)
})
Method (_STA, 0) // Device Status
@@ -77,15 +79,15 @@ Device (LPCB)
If (HPTE) {
CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
If (HPAS == 1) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x1000
+ HPT0 = HPET_BASE_ADDRESS + 0x1000
}
If (HPAS == 2) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x2000
+ HPT0 = HPET_BASE_ADDRESS + 0x2000
}
If (HPAS == 3) {
- HPT0 = CONFIG_HPET_ADDRESS + 0x3000
+ HPT0 = HPET_BASE_ADDRESS + 0x3000
}
}