6 files changed, 9 insertions, 9 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a490540fc5..b58b244607 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -467,7 +467,7 @@ struct soc_intel_alderlake_config {
 
 	bool skip_ext_gfx_scan;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
 	bool eist_enable;
 
 	/* Enable C6 DRAM */
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 1e7e5a5225..97657e2feb 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -237,7 +237,7 @@ struct soc_intel_cannonlake_config {
 	/* Enables support for Teton Glacier hybrid storage device */
 	bool TetonGlacierMode;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
 	bool eist_enable;
 
 	/* Enable C6 DRAM */
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index 5330f223ad..e5c7f54046 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -258,8 +258,8 @@ struct soc_intel_elkhartlake_config {
 	uint8_t Heci2Enable;
 	uint8_t Heci3Enable;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
-	uint8_t eist_enable;
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
+	bool eist_enable;
 
 	/*
 	 * SerialIO device mode selection:
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index f8d069e004..542ccb61cb 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -178,7 +178,7 @@ struct soc_intel_jasperlake_config {
 	/* Gfx related */
 	bool SkipExtGfxScan;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
 	bool eist_enable;
 
 	/* Enable C6 DRAM */
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 7997f7df44..4e0ba86fd7 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -459,8 +459,8 @@ struct soc_intel_skylake_config {
 	u8 SlowSlewRateForSa;
 
 	/* Enable/Disable EIST
-	 * 1b - Enabled
-	 * 0b - Disabled
+	 * true - Enabled
+	 * false - Disabled
 	 */
 	bool eist_enable;
 
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index f8d4d4907b..e8d417e3a8 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -286,8 +286,8 @@ struct soc_intel_tigerlake_config {
 	/* Gfx related */
 	uint8_t SkipExtGfxScan;
 
-	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
-	uint8_t eist_enable;
+	/* Enable/Disable EIST. true:Enabled, false:Disabled */
+	bool eist_enable;
 
 	/* Enable C6 DRAM */
 	uint8_t enable_c6dram;