diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/tigerlake/acpi/pci_irqs.asl | 236 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/irq.h | 60 |
2 files changed, 121 insertions, 175 deletions
diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 536c75a950..6f5f4bc3fd 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -1,146 +1,152 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <soc/irq.h> - Name (PICP, Package () { - /* D31:HDA, SMBUS, TraceHUB */ - Package(){0x001FFFFF, 3, 0, HDA_IRQ }, - Package(){0x001FFFFF, 4, 0, SMBUS_IRQ }, - Package(){0x001FFFFF, 6, 0, GBE_IRQ }, - Package(){0x001FFFFF, 7, 0, TRACEHUB_IRQ }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, - Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, - Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ }, - Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ }, - /* D29: RP9 ~ RP12 */ - Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ }, - Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ }, - Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ }, - Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ }, - /* D28: RP1 ~ RP8 */ - Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ }, - Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, - Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, - Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - Package(){0x001CFFFF, 4, 0, PCIE_5_IRQ }, - Package(){0x001CFFFF, 5, 0, PCIE_6_IRQ }, - Package(){0x001CFFFF, 6, 0, PCIE_7_IRQ }, - Package(){0x001CFFFF, 7, 0, PCIE_8_IRQ }, - /* D25: I2C4, I2C5, UART2 */ - Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, - Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, - Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ }, - /* D23: SATA */ - Package(){0x0017FFFF, 0, 0, SATA_IRQ }, - /* D22: CSME */ - Package(){0x0016FFFF, 0, 0, HECI_1_IRQ }, - Package(){0x0016FFFF, 1, 0, HECI_2_IRQ }, - Package(){0x0016FFFF, 4, 0, HECI_3_IRQ }, - Package(){0x0016FFFF, 5, 0, HECI_4_IRQ }, - /* D21: I2C0 ~ I2C3 */ - Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ }, - Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, - Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, - Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, xDCI, SRAM, CNVI_WIFI */ - Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, - Package(){0x0014FFFF, 3, 0, CNVI_WIFI_IRQ }, - /* D19: SPI3 */ - Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, - /* D18: ISH, SPI2 */ - Package(){0x0012FFFF, 0, 0, ISH_IRQ }, - Package(){0x0012FFFF, 6, 0, LPSS_SPI2_IRQ }, - /* D16: TCH0, TCH1 */ - Package(){0x0010FFFF, 6, 0, THC0_IRQ }, - Package(){0x0010FFFF, 7, 0, THC1_IRQ }, - /* D13: xHCI, xDCI */ - Package(){0x000DFFFF, 0, 0, xHCI_IRQ }, - Package(){0x000DFFFF, 1, 0, xDCI_IRQ }, - /* D8: GNA */ - Package(){0x0008FFFF, 0, 0, GNA_IRQ }, - /* D7: TBT PCIe */ - Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, - Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, - Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, - Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, - /* D6: PEG60 */ - Package(){0x0006FFFF, 0, 0, PEG_IRQ }, - /* D5: IPU Device */ - Package(){0x0005FFFF, 0, 0, IPU_IRQ }, - /* D4: Thermal Device */ - Package(){0x0004FFFF, 0, 0, THERMAL_IRQ }, - /* D2: IGFX */ - Package(){0x0002FFFF, 0, 0, IGFX_IRQ }, + /* D31 */ + Package(){0x001FFFFF, 0, 0, 16 }, + /* D30 */ + Package(){0x001EFFFF, 0, 0, 16 }, + Package(){0x001EFFFF, 1, 0, 17 }, + Package(){0x001EFFFF, 2, 0, 36 }, + Package(){0x001EFFFF, 3, 0, 37 }, + /* D29 */ + Package(){0x001DFFFF, 0, 0, 16 }, + Package(){0x001DFFFF, 1, 0, 17 }, + Package(){0x001DFFFF, 2, 0, 18 }, + Package(){0x001DFFFF, 3, 0, 19 }, + /* D28 */ + Package(){0x001CFFFF, 0, 0, 16 }, + Package(){0x001CFFFF, 1, 0, 17 }, + Package(){0x001CFFFF, 2, 0, 18 }, + Package(){0x001CFFFF, 3, 0, 19 }, + /* D25 */ + Package(){0x0019FFFF, 0, 0, 31 }, + Package(){0x0019FFFF, 1, 0, 32 }, + Package(){0x0019FFFF, 2, 0, 33 }, + /* D23 */ + Package(){0x0017FFFF, 0, 0, 16 }, + /* D22 */ + Package(){0x0016FFFF, 0, 0, 16 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 2, 0, 18 }, + Package(){0x0016FFFF, 3, 0, 19 }, + /* D21 */ + Package(){0x0015FFFF, 0, 0, 27 }, + Package(){0x0015FFFF, 1, 0, 40 }, + Package(){0x0015FFFF, 2, 0, 29 }, + Package(){0x0015FFFF, 3, 0, 30 }, + /* D20 */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + /* D19 */ + Package(){0x0013FFFF, 0, 0, 43 }, + Package(){0x0013FFFF, 1, 0, 24 }, + Package(){0x0013FFFF, 2, 0, 25 }, + Package(){0x0013FFFF, 3, 0, 38 }, + /* D18 */ + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 34 }, + /* D17 */ + Package(){0x0011FFFF, 0, 0, 35 }, + Package(){0x0011FFFF, 1, 0, 20 }, + Package(){0x0011FFFF, 2, 0, 21 }, + Package(){0x0011FFFF, 3, 0, 42 }, + /* D16 */ + Package(){0x0010FFFF, 0, 0, 23 }, + Package(){0x0010FFFF, 1, 0, 22 }, + Package(){0x0010FFFF, 2, 0, 18 }, + Package(){0x0010FFFF, 3, 0, 19 }, + /* D13 */ + Package(){0x000DFFFF, 0, 0, 16 }, + Package(){0x000DFFFF, 1, 0, 17 }, + /* D8 */ + Package(){0x0008FFFF, 0, 0, 16 }, + /* D7 */ + Package(){0x0007FFFF, 0, 0, 16 }, + Package(){0x0007FFFF, 1, 0, 17 }, + Package(){0x0007FFFF, 2, 0, 18 }, + Package(){0x0007FFFF, 3, 0, 19 }, + /* D6 */ + Package(){0x0006FFFF, 0, 0, 16 }, + /* D5 */ + Package(){0x0005FFFF, 0, 0, 16 }, + /* D4 */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* D2 */ + Package(){0x0002FFFF, 0, 0, 16 }, }) Name (PICN, Package () { - /* D31:HDA, SMBUS, TraceHUB*/ - Package () { 0x001FFFFF, 3, 0, 11 }, - Package () { 0x001FFFFF, 4, 0, 11 }, - Package () { 0x001FFFFF, 7, 0, 11 }, - /* D30: UART0, UART1, SPI0, SPI1 */ - Package () { 0x001EFFFF, 0, 0, 11 }, - Package () { 0x001EFFFF, 1, 0, 10 }, - Package () { 0x001EFFFF, 2, 0, 11 }, - Package () { 0x001EFFFF, 3, 0, 11 }, - /* D29: RP9 ~ RP12 */ - Package () { 0x001DFFFF, 0, 0, 11 }, - Package () { 0x001DFFFF, 1, 0, 10 }, - Package () { 0x001DFFFF, 2, 0, 11 }, - Package () { 0x001DFFFF, 3, 0, 11 }, - /* D28: RP1 ~ RP8 */ - Package () { 0x001CFFFF, 0, 0, 11 }, - Package () { 0x001CFFFF, 1, 0, 10 }, - Package () { 0x001CFFFF, 2, 0, 11 }, - Package () { 0x001CFFFF, 3, 0, 11 }, - Package () { 0x001CFFFF, 4, 0, 11 }, - Package () { 0x001CFFFF, 5, 0, 10 }, - Package () { 0x001CFFFF, 6, 0, 11 }, - Package () { 0x001CFFFF, 7, 0, 11 }, - /* D25: I2C4, I2C5, UART2 */ + /* D31 */ + Package(){0x001FFFFF, 0, 0, 11 }, + /* D30 */ + Package(){0x001EFFFF, 0, 0, 11 }, + Package(){0x001EFFFF, 1, 0, 10 }, + Package(){0x001EFFFF, 2, 0, 11 }, + Package(){0x001EFFFF, 3, 0, 11 }, + /* D29 */ + Package(){0x001DFFFF, 0, 0, 11 }, + Package(){0x001DFFFF, 1, 0, 10 }, + Package(){0x001DFFFF, 2, 0, 11 }, + Package(){0x001DFFFF, 3, 0, 11 }, + /* D28 */ + Package(){0x001CFFFF, 0, 0, 11 }, + Package(){0x001CFFFF, 1, 0, 10 }, + Package(){0x001CFFFF, 2, 0, 11 }, + Package(){0x001CFFFF, 3, 0, 11 }, + /* D25 */ Package(){0x0019FFFF, 0, 0, 11 }, Package(){0x0019FFFF, 1, 0, 10 }, Package(){0x0019FFFF, 2, 0, 11 }, - /* D23: SATA */ - Package () { 0x0017FFFF, 0, 0, 11 }, - /* D22: CSME */ + /* D23 */ + Package(){0x0017FFFF, 0, 0, 11 }, + /* D22 */ Package(){0x0016FFFF, 0, 0, 11 }, Package(){0x0016FFFF, 1, 0, 10 }, - Package(){0x0016FFFF, 4, 0, 11 }, - Package(){0x0016FFFF, 5, 0, 11 }, - /* D21: I2C0 ~ I2C3 */ + Package(){0x0016FFFF, 2, 0, 11 }, + Package(){0x0016FFFF, 3, 0, 11 }, + /* D21 */ Package(){0x0015FFFF, 0, 0, 11 }, Package(){0x0015FFFF, 1, 0, 10 }, Package(){0x0015FFFF, 2, 0, 11 }, Package(){0x0015FFFF, 3, 0, 11 }, - /* D19: SPI3 */ + /* D20 */ + Package(){0x0014FFFF, 0, 0, 11 }, + Package(){0x0014FFFF, 0, 0, 10 }, + /* D19 */ Package(){0x0013FFFF, 0, 0, 11 }, - /* D18: ISH, SPI2 */ + Package(){0x0013FFFF, 1, 0, 10 }, + Package(){0x0013FFFF, 2, 0, 11 }, + Package(){0x0013FFFF, 3, 0, 11 }, + /* D18 */ Package(){0x0012FFFF, 0, 0, 11 }, - Package(){0x0012FFFF, 6, 0, 11 },, - /* D16: CNVI_BT, TCH0, TCH1 */ + Package(){0x0012FFFF, 1, 0, 10 },, + /* D18 */ + Package(){0x0011FFFF, 0, 0, 11 }, + Package(){0x0011FFFF, 1, 0, 10 }, + Package(){0x0011FFFF, 2, 0, 11 }, + Package(){0x0011FFFF, 3, 0, 11 }, + /* D16 */ + Package(){0x0010FFFF, 0, 0, 11 }, + Package(){0x0010FFFF, 1, 0, 10 }, Package(){0x0010FFFF, 2, 0, 11 }, - Package(){0x0010FFFF, 6, 0, 11 }, - Package(){0x0010FFFF, 7, 0, 10 }, - /* D13: xHCI, xDCI */ + Package(){0x0010FFFF, 3, 0, 11 }, + /* D13 */ Package(){0x000DFFFF, 0, 0, 11 }, Package(){0x000DFFFF, 1, 0, 10 }, - /* D8: GNA */ + /* D8 */ Package(){0x0008FFFF, 0, 0, 11 }, - /* D7: TBT PCIe */ + /* D7 */ Package(){0x0007FFFF, 0, 0, 11 }, Package(){0x0007FFFF, 1, 0, 10 }, Package(){0x0007FFFF, 2, 0, 11 }, Package(){0x0007FFFF, 3, 0, 11 }, - /* D6: PEG60 */ + /* D6 */ Package(){0x0006FFFF, 0, 0, 11 }, - /* D5: IPU Device */ + /* D5 */ Package(){0x0005FFFF, 0, 0, 11 }, - /* D4: Thermal Device */ + /* D4 */ Package(){0x0004FFFF, 0, 0, 11 }, - /* D2: IGFX */ + /* D2 */ Package(){0x0002FFFF, 0, 0, 11 }, }) diff --git a/src/soc/intel/tigerlake/include/soc/irq.h b/src/soc/intel/tigerlake/include/soc/irq.h index 68428d8ab0..ad70290148 100644 --- a/src/soc/intel/tigerlake/include/soc/irq.h +++ b/src/soc/intel/tigerlake/include/soc/irq.h @@ -9,64 +9,4 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 -#define LPSS_I2C0_IRQ 27 -#define LPSS_I2C1_IRQ 40 -#define LPSS_I2C2_IRQ 29 -#define LPSS_I2C3_IRQ 30 -#define LPSS_I2C4_IRQ 31 -#define LPSS_I2C5_IRQ 32 -#define LPSS_SPI0_IRQ 36 -#define LPSS_SPI1_IRQ 37 -#define LPSS_SPI2_IRQ 34 -#define LPSS_SPI3_IRQ 43 -#define LPSS_UART0_IRQ 16 -#define LPSS_UART1_IRQ 17 -#define LPSS_UART2_IRQ 33 - -#define HDA_IRQ 16 -#define GBE_IRQ 16 -#define SMBUS_IRQ 16 -#define TRACEHUB_IRQ 16 - -#define PCIE_1_IRQ 16 -#define PCIE_2_IRQ 17 -#define PCIE_3_IRQ 18 -#define PCIE_4_IRQ 19 -#define PCIE_5_IRQ 16 -#define PCIE_6_IRQ 17 -#define PCIE_7_IRQ 18 -#define PCIE_8_IRQ 19 -#define PCIE_9_IRQ 16 -#define PCIE_10_IRQ 17 -#define PCIE_11_IRQ 18 -#define PCIE_12_IRQ 19 - -#define SATA_IRQ 16 - -#define xHCI_IRQ 16 -#define xDCI_IRQ 17 -#define CNVI_WIFI_IRQ 16 - -#define CNVI_BT_IRQ 18 - -#define THC0_IRQ 23 -#define THC1_IRQ 22 - -#define ISH_IRQ 16 - -#define TBT_PCIe0_IRQ 16 -#define TBT_PCIe1_IRQ 17 -#define TBT_PCIe2_IRQ 18 -#define TBT_PCIe3_IRQ 19 - -#define HECI_1_IRQ 16 -#define HECI_2_IRQ 17 -#define HECI_3_IRQ 16 -#define HECI_4_IRQ 19 - -#define PEG_IRQ 16 -#define IGFX_IRQ 16 -#define THERMAL_IRQ 16 -#define IPU_IRQ 16 -#define GNA_IRQ 16 #endif /* _SOC_IRQ_H_ */ |