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-rw-r--r--src/soc/intel/elkhartlake/acpi/tsn_glan.asl28
-rw-r--r--src/soc/intel/elkhartlake/chip.c4
-rw-r--r--src/soc/intel/elkhartlake/chip.h22
-rw-r--r--src/soc/intel/elkhartlake/fsp_params.c101
4 files changed, 116 insertions, 39 deletions
diff --git a/src/soc/intel/elkhartlake/acpi/tsn_glan.asl b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl
index de4f0b66a4..eb5fed89fe 100644
--- a/src/soc/intel/elkhartlake/acpi/tsn_glan.asl
+++ b/src/soc/intel/elkhartlake/acpi/tsn_glan.asl
@@ -13,3 +13,31 @@ Device(GTSN) {
TADH, 32,
}
}
+
+/* Intel PSE TSN Ethernet Controller #1 0:1d.1 */
+
+Device(OTN0) {
+ Name(_ADR, 0x001D0001)
+ OperationRegion(TSRT,PCI_Config,0x00,0x100)
+ Field(TSRT,AnyAcc,NoLock,Preserve)
+ {
+ DVID, 16,
+ Offset(0x10),
+ TADL, 32,
+ TADH, 32,
+ }
+}
+
+/* Intel PSE TSN Ethernet Controller #2 0:1d.2 */
+
+Device(OTN1) {
+ Name(_ADR, 0x001D0002)
+ OperationRegion(TSRT,PCI_Config,0x00,0x100)
+ Field(TSRT,AnyAcc,NoLock,Preserve)
+ {
+ DVID, 16,
+ Offset(0x10),
+ TADL, 32,
+ TADH, 32,
+ }
+}
diff --git a/src/soc/intel/elkhartlake/chip.c b/src/soc/intel/elkhartlake/chip.c
index ad634819f2..3bed78bece 100644
--- a/src/soc/intel/elkhartlake/chip.c
+++ b/src/soc/intel/elkhartlake/chip.c
@@ -82,11 +82,13 @@ const char *soc_acpi_name(const struct device *dev)
case PCH_DEVFN_PCIE5: return "RP05";
case PCH_DEVFN_PCIE6: return "RP06";
case PCH_DEVFN_PCIE7: return "RP07";
+ case PCH_DEVFN_PSEGBE0: return "OTN0";
+ case PCH_DEVFN_PSEGBE1: return "OTN1";
case PCH_DEVFN_UART0: return "UAR0";
case PCH_DEVFN_UART1: return "UAR1";
case PCH_DEVFN_GSPI0: return "SPI0";
case PCH_DEVFN_GSPI1: return "SPI1";
- case PCH_DEVFN_GBE: return "GLAN";
+ case PCH_DEVFN_GBE: return "GTSN";
case PCH_DEVFN_GSPI2: return "SPI2";
case PCH_DEVFN_EMMC: return "EMMC";
case PCH_DEVFN_SDCARD: return "SDXC";
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h
index a4e8cadb8d..3e1d56e17e 100644
--- a/src/soc/intel/elkhartlake/chip.h
+++ b/src/soc/intel/elkhartlake/chip.h
@@ -23,6 +23,7 @@
#define MAX_HD_AUDIO_DMIC_LINKS 2
#define MAX_HD_AUDIO_SNDW_LINKS 4
#define MAX_HD_AUDIO_SSP_LINKS 6
+#define MAX_PSE_TSN_PORTS 2
/* Define config parameters for In-Band ECC (IBECC). */
#define MAX_IBECC_REGIONS 8
@@ -48,6 +49,13 @@ enum tsn_gbe_link_speed {
Tsn_1_Gbps,
};
+/* TSN Phy Interface Type: 1: RGMII, 2: SGMII, 3:SGMII+ */
+enum tsn_phy_type {
+ RGMII = 1,
+ SGMII = 2,
+ SGMII_plus = 3,
+};
+
/*
* PSE native pins and ownership assignment:-
* 0: Disable/pins are not owned by PSE/host
@@ -458,13 +466,18 @@ struct soc_intel_elkhartlake_config {
*/
u8 PchPmPwrBtnOverridePeriod;
- /* GBE related */
- /* PCH TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */
+ /* GBE related (PCH & PSE) */
+ /* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */
enum tsn_gbe_link_speed PchTsnGbeLinkSpeed;
- /* PCH TSN GBE SGMII Support: Disable (0) / Enable (1) */
+ enum tsn_gbe_link_speed PseTsnGbeLinkSpeed[MAX_PSE_TSN_PORTS];
+ /* TSN GBE SGMII Support: Disable (0) / Enable (1) */
bool PchTsnGbeSgmiiEnable;
- /* PCH TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */
+ bool PseTsnGbeSgmiiEnable[MAX_PSE_TSN_PORTS];
+ /* TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */
bool PchTsnGbeMultiVcEnable;
+ bool PseTsnGbeMultiVcEnable[MAX_PSE_TSN_PORTS];
+ /* PSE TSN Phy Interface Type */
+ enum tsn_phy_type PseTsnGbePhyType[MAX_PSE_TSN_PORTS];
/* PSE related */
/*
@@ -490,6 +503,7 @@ struct soc_intel_elkhartlake_config {
enum pse_device_ownership PseCanOwn[2];
enum pse_device_ownership PsePwmOwn;
enum pse_device_ownership PseAdcOwn;
+ enum pse_device_ownership PseGbeOwn[MAX_PSE_TSN_PORTS];
/* PSE devices sideband interrupt: Disable (0) / Enable (1) */
bool PseDmaSbIntEn[3];
bool PseUartSbIntEn[6];
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c
index fc5ea1c873..1584c6af6c 100644
--- a/src/soc/intel/elkhartlake/fsp_params.c
+++ b/src/soc/intel/elkhartlake/fsp_params.c
@@ -79,6 +79,70 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
s_cfg->FivrSpreadSpectrum = config->fivr.spread_spectrum;
}
+static void fill_fsps_tsn_params(FSP_S_CONFIG *params,
+ const struct soc_intel_elkhartlake_config *config)
+{
+ /*
+ * Currently EHL TSN GBE only supports link speed with 2 type of
+ * PCH XTAL frequency: 24 MHz and 38.4 MHz.
+ * These are the config values for PchTsnGbeLinkSpeed in FSP-S UPD:
+ * 0: 24MHz 2.5Gbps, 1: 24MHz 1Gbps, 2: 38.4MHz 2.5Gbps,
+ * 3: 38.4MHz 1Gbps
+ */
+ int xtal_freq_enum = pmc_get_xtal_freq();
+ if ((xtal_freq_enum != XTAL_24_MHZ) && (xtal_freq_enum != XTAL_38_4_MHZ)) {
+ printk(BIOS_ERR, "XTAL not supported. Disabling All TSN GBE ports.\n");
+ params->PchTsnEnable = 0;
+ params->PchPseGbeEnable[0] = 0;
+ params->PchPseGbeEnable[1] = 0;
+ devfn_disable(pci_root_bus(), PCH_DEVFN_GBE);
+ devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE0);
+ devfn_disable(pci_root_bus(), PCH_DEVFN_PSEGBE1);
+ }
+ /*
+ * PCH TSN settings:
+ * Due to EHL GBE comes with time sensitive networking (TSN)
+ * capability integrated, EHL FSP is using PchTsnEnable instead of
+ * usual PchLanEnable flag for GBE control. Hence, force
+ * PchLanEnable to disable to avoid it being used in the future.
+ */
+ params->PchLanEnable = 0x0;
+ params->PchTsnEnable = is_devfn_enabled(PCH_DEVFN_GBE);
+ if (params->PchTsnEnable) {
+ params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable;
+ params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable;
+ params->PchTsnGbeLinkSpeed = (config->PchTsnGbeLinkSpeed) + xtal_freq_enum;
+ }
+
+ /* PSE TSN settings */
+ if (!CONFIG(PSE_ENABLE))
+ return;
+ for (unsigned int i = 0; i < MAX_PSE_TSN_PORTS; i++) {
+ switch (i) {
+ case 0:
+ params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE0) ?
+ Host_Owned : config->PseGbeOwn[0];
+ break;
+ case 1:
+ params->PchPseGbeEnable[i] = is_devfn_enabled(PCH_DEVFN_PSEGBE1) ?
+ Host_Owned : config->PseGbeOwn[i];
+ break;
+ default:
+ break;
+ }
+ if (params->PchPseGbeEnable[i]) {
+ params->PseTsnGbeMultiVcEnable[i] = config->PseTsnGbeMultiVcEnable[i];
+ params->PseTsnGbeSgmiiEnable[i] = config->PseTsnGbeSgmiiEnable[i];
+ params->PseTsnGbePhyInterfaceType[i] =
+ !!config->PseTsnGbeSgmiiEnable[i] ?
+ RGMII : config->PseTsnGbePhyType[i];
+ params->PseTsnGbeLinkSpeed[i] =
+ (params->PseTsnGbePhyInterfaceType[i] < SGMII_plus) ?
+ xtal_freq_enum + 1 : xtal_freq_enum;
+ }
+ }
+}
+
static void fill_fsps_pse_params(FSP_S_CONFIG *params,
const struct soc_intel_elkhartlake_config *config)
{
@@ -397,44 +461,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PsfFusaConfigEnable = 0;
}
- /* PCH GBE config */
- /*
- * Due to EHL GBE comes with time sensitive networking (TSN)
- * capability integrated, EHL FSP is using PchTsnEnable instead of
- * usual PchLanEnable flag for GBE control. Hence, force
- * PchLanEnable to disable to avoid it being used in the future.
- */
- params->PchLanEnable = 0x0;
- params->PchTsnEnable = is_devfn_enabled(PCH_DEVFN_GBE);
- if (params->PchTsnEnable) {
- params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable;
- params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable;
- /*
- * Currently EHL TSN GBE only supports link speed with 2 type of
- * PCH XTAL frequency: 24 MHz and 38.4 MHz.
- * These are the configs setup for PchTsnGbeLinkSpeed FSP-S UPD:
- * 0: 24MHz 2.5Gbps, 1: 24MHz 1Gbps, 2: 38.4MHz 2.5Gbps,
- * 3: 38.4MHz 1Gbps
- */
- switch (pmc_get_xtal_freq()) {
- case XTAL_24_MHZ:
- params->PchTsnGbeLinkSpeed = (!!config->PchTsnGbeLinkSpeed);
- break;
- case XTAL_38_4_MHZ:
- params->PchTsnGbeLinkSpeed = (!!config->PchTsnGbeLinkSpeed) + 0x2;
- break;
- case XTAL_19_2_MHZ:
- default:
- printk(BIOS_ERR, "XTAL not supported. Disabling PCH TSN GBE.\n");
- params->PchTsnEnable = 0;
- devfn_disable(pci_root_bus(), PCH_DEVFN_GBE);
- }
- }
-
/* PSE (Intel Programmable Services Engine) config */
if (CONFIG(PSE_ENABLE) && cbfs_file_exists("pse.bin"))
fill_fsps_pse_params(params, config);
+ /* TSN GBE config */
+ fill_fsps_tsn_params(params, config);
+
/* Override/Fill FSP Silicon Param for mainboard */
mainboard_silicon_init_params(params);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 01:40:00 +0000