diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index c64af02bba..179cd43e3a 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -25,8 +25,8 @@ #include <soc/intel/broadwell/chip.h> #include <cpu/intel/common/common.h> -/* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate - * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly +/* The core 100MHz BCLK is disabled in deeper c-states. One needs to calibrate + * the 100MHz BCLK against the 24MHz BCLK to restore the clocks properly * when a core is woken up. */ static int pcode_ready(void) { @@ -65,7 +65,7 @@ static void calibrate_24mhz_bclk(void) err_code = MCHBAR32(BIOS_MAILBOX_INTERFACE) & 0xff; - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration response: %d\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration response: %d\n", err_code); /* Read the calibrated value. */ @@ -77,7 +77,7 @@ static void calibrate_24mhz_bclk(void) return; } - printk(BIOS_DEBUG, "PCODE: 24MHz BLCK calibration value: 0x%08x\n", + printk(BIOS_DEBUG, "PCODE: 24MHz BCLK calibration value: 0x%08x\n", MCHBAR32(BIOS_MAILBOX_DATA)); } |