diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/amd/cezanne/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/soc/amd/common/psp_verstage/Kconfig | 11 |
2 files changed, 13 insertions, 2 deletions
diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 58df7406ed..a05da8dc76 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -110,6 +110,10 @@ else PSP_SOFTFUSE_BITS += 29 endif +ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y) +PSP_SOFTFUSE_BITS += 40 +endif + # Use additional Soft Fuse bits specified in Kconfig PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS)) diff --git a/src/soc/amd/common/psp_verstage/Kconfig b/src/soc/amd/common/psp_verstage/Kconfig index 6cac8b70ed..45a5d22423 100644 --- a/src/soc/amd/common/psp_verstage/Kconfig +++ b/src/soc/amd/common/psp_verstage/Kconfig @@ -6,10 +6,17 @@ config PSP_VERSTAGE_CCP_DMA accessing the boot device. Select it on platforms which supports using CCP DMA to access the boot device. +config PSP_S0I3_RESUME_VERSTAGE + bool "S0i3 resume verstage" + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + default n + help + Select this item to enable running verstage during S0i3 resume. + config PSP_INIT_TPM_ON_S0I3_RESUME bool - depends on TPM2 && VBOOT_STARTS_BEFORE_BOOTBLOCK - default VBOOT_STARTS_BEFORE_BOOTBLOCK + depends on TPM2 && PSP_S0I3_RESUME_VERSTAGE + default PSP_S0I3_RESUME_VERSTAGE help If the TPM is reset while in S0i3, it must be reinitialized during s0i3 resume. This must be performed in PSP verstage since |