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-rw-r--r--src/soc/intel/cannonlake/fsp_params.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 74884fde1f..0713ef4604 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -460,6 +460,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SpiFlashCfgLockDown = 1;
#endif
}
+
+ dev = pcidev_path_on_root(SA_DEVFN_IGD);
+ if (CONFIG(RUN_FSP_GOP) && dev && dev->enabled)
+ params->PeiGraphicsPeimInit = 1;
+ else
+ params->PeiGraphicsPeimInit = 0;
}
/* Mainboard GPIO Configuration */