diff options
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/skylake/chip.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/skylake/chip.h | 3 |
2 files changed, 7 insertions, 4 deletions
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b731baff8d..b24ec4fdc0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -258,9 +258,15 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; - params->SataPwrOptEnable = config->SataPwrOptEnable; params->EnableTcoTimer = !config->PmTimerDisabled; + /* + * For unknown reasons FSP skips writing some essential SATA init registers (SIR) when + * SataPwrOptEnable=0. This results in link errors, "unaligned write" errors and others. + * Enabling this option solves these problems. + */ + params->SataPwrOptEnable = 1; + tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 387bd6fe3d..d268eebd66 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -567,9 +567,6 @@ struct soc_intel_skylake_config { */ u8 IslVrCmd; - /* Enable/Disable Sata power optimization */ - u8 SataPwrOptEnable; - /* Enable/Disable Sata test mode */ u8 SataTestMode; |