3 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index f02af1f6b5..342edb5937 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -78,6 +78,14 @@ config COS_MAPPED_TO_MSB
 	  On TGL and JSL platform the class of service configuration
 	  is mapped to MSB of MSR IA32_PQR_ASSOC.
 
+config CAR_HAS_L3_PROTECTED_WAYS
+	bool
+	depends on INTEL_CAR_NEM_ENHANCED
+	help
+	  On ADL and onwards platform has a newer requirement to protect
+	  L3 ways in Non-Inclusive eNEM mode. Hence, MSR 0xc85 is to program
+	  the data ways.
+
 config USE_INTEL_FSP_MP_INIT
 	bool "Perform MP Initialization by FSP"
 	default n
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 74c1860cae..f0c3149833 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -567,6 +567,13 @@ program_sf2:
 	movl	$IA32_CR_SF_QOS_MASK_1, %ecx
 	wrmsr
 #endif
+#if CONFIG(CAR_HAS_L3_PROTECTED_WAYS)
+	/* Set MSR 0xC85 L3_Protected_ways = ((1 << data ways) - 1) */
+	mov	%esi, %eax
+	xorl	%edx, %edx
+	mov	$IA32_L3_PROTECTED_WAYS, %ecx
+	wrmsr
+#endif
 	/*
 	 * Program MSR 0xC91 IA32_L3_MASK_1
 	 * This MSR contain one bit per each way of LLC
diff --git a/src/soc/intel/common/block/cpu/car/exit_car.S b/src/soc/intel/common/block/cpu/car/exit_car.S
index 191232a3b0..cfb1ab5a79 100644
--- a/src/soc/intel/common/block/cpu/car/exit_car.S
+++ b/src/soc/intel/common/block/cpu/car/exit_car.S
@@ -96,6 +96,13 @@ car_nem_enhanced_teardown:
 	rdmsr
 	and	$~IA32_PQR_ASSOC_MASK, %edx
 	wrmsr
+#if CONFIG(CAR_HAS_L3_PROTECTED_WAYS)
+	/* Set MSR 0xC85 L3_Protected_ways = 0x00000 */
+	mov	$IA32_L3_PROTECTED_WAYS, %ecx
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	wrmsr
+#endif
 #endif
 
 	/* Return to caller. */