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-rw-r--r--src/soc/rockchip/rk3399/chip.h1
-rw-r--r--src/soc/rockchip/rk3399/display.c28
-rw-r--r--src/soc/rockchip/rk3399/include/soc/display.h3
-rw-r--r--src/soc/rockchip/rk3399/include/soc/memlayout.ld1
-rw-r--r--src/soc/rockchip/rk3399/soc.c3
5 files changed, 12 insertions, 24 deletions
diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h
index 46baa8ccea..1f9462a009 100644
--- a/src/soc/rockchip/rk3399/chip.h
+++ b/src/soc/rockchip/rk3399/chip.h
@@ -20,7 +20,6 @@
#include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */
struct soc_rockchip_rk3399_config {
- u32 vop_id;
gpio_t lcd_bl_pwm_gpio;
gpio_t lcd_bl_en_gpio;
u32 bl_power_on_udelay;
diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c
index 267986090f..372e115cf4 100644
--- a/src/soc/rockchip/rk3399/display.c
+++ b/src/soc/rockchip/rk3399/display.c
@@ -36,20 +36,14 @@
#include "chip.h"
-void rk_display_init(device_t dev, uintptr_t lcdbase,
- unsigned long fb_size)
+void rk_display_init(device_t dev)
{
struct edid edid;
- uint32_t val;
struct soc_rockchip_rk3399_config *conf = dev->chip_info;
- uintptr_t lower = ALIGN_DOWN(lcdbase, MiB);
- uintptr_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
enum vop_modes detected_mode = VOP_MODE_UNKNOWN;
- printk(BIOS_DEBUG, "LCD framebuffer @%p\n", (void *)(lcdbase));
- memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */
- dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
- mmu_config_range((void *)lower, upper - lower, UNCACHED_MEM);
+ /* let's use vop0 in rk3399 */
+ uint32_t vop_id = 0;
switch (conf->vop_mode) {
case VOP_MODE_NONE:
@@ -58,12 +52,10 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
/* try EDP first, then HDMI */
case VOP_MODE_EDP:
printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
- rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
+ rkclk_configure_vop_aclk(vop_id, 192 * MHz);
- /* select edp signal from vop0(big) or vop1(little) */
- val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) :
- RK_CLRBITS(1 << 5);
- write32(&rk3399_grf->soc_con20, val);
+ /* select edp signal from vop0 */
+ write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
/* select edp clk from SoC internal 24M crystal, otherwise,
* it will source from edp's 24M clock (that depends on
@@ -89,7 +81,7 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
return;
}
- if (rkclk_configure_vop_dclk(conf->vop_id,
+ if (rkclk_configure_vop_dclk(vop_id,
edid.mode.pixel_clock * KHz)) {
printk(BIOS_WARNING, "config vop err\n");
return;
@@ -97,9 +89,9 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
edid_set_framebuffer_bits_per_pixel(&edid,
conf->framebuffer_bits_per_pixel, 0);
- rkvop_mode_set(conf->vop_id, &edid, detected_mode);
+ rkvop_mode_set(vop_id, &edid, detected_mode);
- rkvop_enable(conf->vop_id, lcdbase, &edid);
+ rkvop_prepare(vop_id, &edid);
switch (detected_mode) {
case VOP_MODE_HDMI:
@@ -115,5 +107,5 @@ void rk_display_init(device_t dev, uintptr_t lcdbase,
break;
}
- set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase);
+ set_vbe_mode_info_valid(&edid, (uintptr_t)0);
}
diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h
index 7ccde5611a..c10f1b9f04 100644
--- a/src/soc/rockchip/rk3399/include/soc/display.h
+++ b/src/soc/rockchip/rk3399/include/soc/display.h
@@ -18,8 +18,7 @@
#define REF_CLK_24M (0x1 << 0)
-void rk_display_init(device_t dev, uintptr_t lcdbase,
- unsigned long fb_size);
+void rk_display_init(device_t dev);
void mainboard_power_on_backlight(void);
#endif
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index a441281de9..f440dfb391 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -22,7 +22,6 @@ SECTIONS
POSTRAM_CBFS_CACHE(0x00100000, 1M)
RAMSTAGE(0x00300000, 256K)
DMA_COHERENT(0x10000000, 2M)
- FRAMEBUFFER(0x10200000, 16M)
/* 8K of special SRAM in PMU power domain. */
SYMBOL(pmu_sram, 0xFF3B0000)
diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c
index 12c757f1ea..e34ca09d06 100644
--- a/src/soc/rockchip/rk3399/soc.c
+++ b/src/soc/rockchip/rk3399/soc.c
@@ -39,8 +39,7 @@ static void soc_init(device_t dev)
mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB));
if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required())
- rk_display_init(dev, (uintptr_t)_framebuffer,
- _framebuffer_size);
+ rk_display_init(dev);
else
printk(BIOS_INFO, "Display initialization disabled.\n");