diff options
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/addressmap.h | 58 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/clock.h | 21 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/memlayout.ld | 36 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/sdram.h | 20 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/timer.h | 39 |
5 files changed, 174 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h new file mode 100644 index 0000000000..377256ed29 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ +#define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ + +#define PMUGRF_BASE 0xff320000 +#define PMUSGRF_BASE 0xff330000 +#define CRU_BASE 0xff760000 +#define GRF_BASE 0xff770000 +#define TIMER0_BASE 0xff850000 +#define EMMC_BASE 0xfe330000 +#define SDMMC_BASE 0xfe320000 + +#define GPIO0_BASE 0xff720000 +#define GPIO1_BASE 0xff730000 +#define GPIO2_BASE 0xff780000 +#define GPIO3_BASE 0xff788000 +#define GPIO4_BASE 0xff790000 + +#define I2C0_BASE 0xff3c0000 +#define I2C1_BASE 0xff110000 +#define I2C2_BASE 0xff120000 +#define I2C3_BASE 0xff130000 +#define I2C4_BASE 0xff3d0000 +#define I2C5_BASE 0xff140000 +#define I2C6_BASE 0xff150000 +#define I2C7_BASE 0xff160000 +#define I2C8_BASE 0xff3e0000 + +#define UART0_BASE 0xff180000 +#define UART1_BASE 0xff190000 +#define UART2_BASE 0xff1a0000 +#define UART3_BASE 0xff1b0000 +#define UART4_BASE 0xff370000 + +#define SPI0_BASE 0xff1c0000 +#define SPI1_BASE 0xff1d0000 +#define SPI2_BASE 0xff1e0000 +#define SPI3_BASE 0xff350000 +#define SPI4_BASE 0xff1f0000 +#define SPI5_BASE 0xff200000 + +#define TSADC_BASE 0xff260000 +#define SARADC_BASE 0xff100000 +#endif /* __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ */ diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h new file mode 100644 index 0000000000..c0ba52c4da --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_CLOCK_H__ +#define __SOC_ROCKCHIP_RK3399_CLOCK_H__ + +void rkclk_configure_spi(unsigned int bus, unsigned int hz); + +#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */ diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld new file mode 100644 index 0000000000..edb246d6f0 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + POSTRAM_CBFS_CACHE(0x00100000, 1M) + RAMSTAGE(0x00300000, 256K) + DMA_COHERENT(0x10000000, 2M) + + SRAM_START(0xFF8C0000) + BOOTBLOCK(0xFF8C2004, 32K - 4) + PRERAM_CBFS_CACHE(0xFF8CA000, 4K) + PRERAM_CBMEM_CONSOLE(0xFF8CB000, 4K) + OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 64K) + VBOOT2_WORK(0XFF8DC000, 12K) + TTB(0xFF8DF000, 32K) + TIMESTAMP(0xFF8E7000, 1K) + STACK(0xFF8E7400, 24K) + SRAM_END(0xFF8F0000) +} diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h new file mode 100644 index 0000000000..808393ceff --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* dummy until the RAM init implementation passed review */ +static int sdram_size_mb(void) +{ + return 0; +} diff --git a/src/soc/rockchip/rk3399/include/soc/timer.h b/src/soc/rockchip/rk3399/include/soc/timer.h new file mode 100644 index 0000000000..8513cfa5bc --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/timer.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_TIMER_H__ +#define __SOC_ROCKCHIP_RK3399_TIMER_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> +#include <timer.h> + +static const u32 clocks_per_usec = (24 * 1000 * 1000) / USECS_PER_SEC; + +struct rk3399_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_cur_value0; + u32 timer_cur_value1; + u32 timer_load_count2; + u32 timer_load_count3; + u32 timer_int_status; + u32 timer_ctrl_reg; +}; + +static struct rk3399_timer * const timer0_ptr = (void *)TIMER0_BASE; +#define TIMER_LOAD_VAL 0xffffffff + +#endif /* __SOC_ROCKCHIP_RK3399_TIMER_H__ */ |