diff options
Diffstat (limited to 'src/soc/rockchip/rk3288')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3288/sdram.c | 3 |
2 files changed, 0 insertions, 5 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index 5b1350a4f6..c3a9ac2a2a 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -304,7 +304,6 @@ void rkclk_init(void) write32(&cru_ptr->cru_mode_con, RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) | RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM)); - } void rkclk_configure_cpu(enum apll_frequencies apll_freq) @@ -665,5 +664,4 @@ unsigned int rkclk_i2c_clock_for_bus(unsigned int bus) default: return -1; /* Should never happen. */ } - } diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 2efe19bd2c..0237ca26f2 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -683,7 +683,6 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) for (i = 0; i < 4; i++) clrbits32(&ddr_publ_regs->datx8[i].dxgcr, DQSRTT | DQRTT); - } } @@ -798,7 +797,6 @@ static void set_bandwidth_ratio(u32 channel, u32 n) DXDLLCR_DLLSRST); } setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2); - } static int data_training(u32 channel, @@ -1074,7 +1072,6 @@ size_t sdram_size_mb(void) u32 ch; if (!size_mb) { - u32 sys_reg = read32(&rk3288_pmu->sys_reg[2]); u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg); |