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-rw-r--r--src/soc/qualcomm/sdm845/include/soc/addressmap.h31
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/aop.h8
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/clock.h194
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/efuse.h17
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/gpio.h339
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/mmu.h8
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/qspi.h108
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/symbols.h17
-rw-r--r--src/soc/qualcomm/sdm845/include/soc/usb.h83
9 files changed, 0 insertions, 805 deletions
diff --git a/src/soc/qualcomm/sdm845/include/soc/addressmap.h b/src/soc/qualcomm/sdm845/include/soc/addressmap.h
deleted file mode 100644
index aa80a1439e..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/addressmap.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
-#define __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__
-
-#define QSPI_BASE 0x88DF000
-#define TLMM_EAST_TILE_BASE 0x03500000
-#define TLMM_NORTH_TILE_BASE 0x03900000
-#define TLMM_SOUTH_TILE_BASE 0x03D00000
-#define GCC_BASE 0x00100000
-
-/*
- * USB BASE ADDRESSES
- */
-#define QFPROM_BASE 0x00780000
-#define QUSB_PRIM_PHY_BASE 0x088e2000
-#define QUSB_PRIM_PHY_DIG_BASE 0x088e2200
-#define QUSB_SEC_PHY_BASE 0x088e3000
-#define QUSB_SEC_PHY_DIG_BASE 0x088e3200
-#define QMP_PHY_QSERDES_COM_REG_BASE 0x088e9000
-#define QMP_PHY_QSERDES_TX_REG_BASE 0x088e9200
-#define QMP_PHY_QSERDES_RX_REG_BASE 0x088e9400
-#define QMP_PHY_PCS_REG_BASE 0x088e9c00
-#define QMP_UNIPHY_QSERDES_COM_REG_BASE 0x088eb000
-#define QMP_UNIPHY_QSERDES_TX_REG_BASE 0x088eb200
-#define QMP_UNIPHY_QSERDES_RX_REG_BASE 0x088eb400
-#define QMP_UNIPHY_PCS_REG_BASE 0x088eb800
-#define USB_HOST0_DWC3_BASE 0x0a60c100
-#define USB_HOST1_DWC3_BASE 0x0a80c100
-
-#endif /* __SOC_QUALCOMM_SDM845_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sdm845/include/soc/aop.h b/src/soc/qualcomm/sdm845/include/soc/aop.h
deleted file mode 100644
index 2f82747486..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/aop.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_QUALCOMM_SDM845_AOP_H__
-#define _SOC_QUALCOMM_SDM845_AOP_H__
-
-void aop_fw_load_reset(void);
-
-#endif // _SOC_QUALCOMM_SDM845_AOP_H__
diff --git a/src/soc/qualcomm/sdm845/include/soc/clock.h b/src/soc/qualcomm/sdm845/include/soc/clock.h
deleted file mode 100644
index 78d5dfd22d..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/clock.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <soc/addressmap.h>
-#include <types.h>
-
-#ifndef __SOC_QUALCOMM_SDM845_CLOCK_H__
-#define __SOC_QUALCOMM_SDM845_CLOCK_H__
-
-#define QUPV3_WRAP_0_M_AHB_CLK_ENA 6
-#define QUPV3_WRAP_0_S_AHB_CLK_ENA 7
-#define QUPV3_WRAP0_CORE_2X_CLK_ENA 9
-#define QUPV3_WRAP0_CORE_CLK_ENA 8
-#define QUPV3_WRAP1_CORE_2X_CLK_ENA 18
-#define QUPV3_WRAP1_CORE_CLK_ENA 19
-#define QUPV3_WRAP_1_M_AHB_CLK_ENA 20
-#define QUPV3_WRAP_1_S_AHB_CLK_ENA 21
-#define QUPV3_WRAP0_CLK_ENA_S(idx) (10 + idx)
-#define QUPV3_WRAP1_CLK_ENA_S(idx) (22 + idx)
-
-#define GPLL0_EVEN_HZ (300*MHz)
-#define GPLL0_MAIN_HZ (600*MHz)
-#define QUP_WRAP_CORE_2X_19_2MHZ (19200*KHz)
-
-#define SRC_XO_19_2MHZ 0
-#define SRC_GPLL0_MAIN_600MHZ 1
-#define SRC_GPLL0_EVEN_300MHZ 6
-
-#define AOP_RESET_SHFT 0
-#define RCG_MODE_DUAL_EDGE 2
-
-struct sdm845_rcg {
- u32 cmd;
- u32 cfg;
-};
-
-struct sdm845_clock {
- u32 cbcr;
- struct sdm845_rcg rcg;
- u32 m;
- u32 n;
- u32 d_2;
-};
-
-struct sdm845_qupv3_clock {
- struct sdm845_clock clk;
- u8 _res[0x130 - 0x18];
-};
-
-struct sdm845_gpll {
- u32 mode;
- u32 l_val;
- u32 cal_l_val;
- u32 user_ctl;
- u32 user_ctl_u;
- u32 config_ctl;
- u32 config_ctl_u;
- u32 test_ctl;
- u32 test_ctl_u;
- u8 _res[0x1000 - 0x24];
-};
-
-struct sdm845_gcc {
- struct sdm845_gpll gpll0;
- u8 _res0[0xf000 - 0x1000];
- u32 usb30_prim_bcr;
- u8 _res1[0x10000 - 0xf004];
- u32 usb30_sec_bcr;
- u8 _res2[0x12000 - 0x10004];
- u32 qusb2phy_prim_bcr;
- u32 qusb2phy_sec_bcr;
- u8 _res3[0x17000 - 0x12008];
- u32 qup_wrap0_bcr;
- u32 qup_wrap0_m_ahb_cbcr;
- u32 qup_wrap0_s_ahb_cbcr;
- u32 qup_wrap0_core_cbcr;
- u32 qup_wrap0_core_cdivr;
- u32 qup_wrap0_core_2x_cbcr;
- struct sdm845_rcg qup_wrap0_core_2x;
- u8 _res4[0x17030 - 0x17020];
- struct sdm845_qupv3_clock qup_wrap0_s[8];
- u8 _res5[0x18000 - 0x179b0];
- u32 qup_wrap1_bcr;
- u32 qup_wrap1_core_2x_cbcr;
- u32 qup_wrap1_core_cbcr;
- u32 qup_wrap1_m_ahb_cbcr;
- u32 qup_wrap1_s_ahb_cbcr;
- struct sdm845_qupv3_clock qup_wrap1_s[8];
- u32 qup_wrap1_core_cdivr;
- u8 _res6[0x4B000 - 0x18998];
- u32 qspi_cnoc_ahb_cbcr;
- u32 qspi_core_cbcr;
- struct sdm845_rcg qspi_core;
- u8 _res7[0x50000-0x4b010];
- u32 usb3_phy_prim_bcr;
- u32 usb3phy_phy_prim_bcr;
- u32 usb3_dp_phy_prim_bcr;
- u32 usb3_phy_sec_bcr;
- u32 usb3phy_phy_sec_bcr;
- u8 _res8[0x5200c-0x50014];
- u32 apcs_clk_br_en1;
- u8 _res9[0x1000000-0x52010];
-};
-check_member(sdm845_gcc, usb30_prim_bcr, 0xf000);
-check_member(sdm845_gcc, usb30_sec_bcr, 0x10000);
-check_member(sdm845_gcc, qusb2phy_prim_bcr, 0x12000);
-check_member(sdm845_gcc, qusb2phy_sec_bcr, 0x12004);
-check_member(sdm845_gcc, usb3phy_phy_prim_bcr, 0x50004);
-check_member(sdm845_gcc, usb3_phy_prim_bcr, 0x50000);
-check_member(sdm845_gcc, usb3_phy_sec_bcr, 0x5000c);
-check_member(sdm845_gcc, usb3phy_phy_sec_bcr, 0x50010);
-check_member(sdm845_gcc, apcs_clk_br_en1, 0x5200c);
-
-enum clk_ctl_gpll_user_ctl {
- CLK_CTL_GPLL_PLLOUT_EVEN_BMSK = 0x2,
- CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0,
- CLK_CTL_GPLL_PLLOUT_EVEN_SHFT = 1,
- CLK_CTL_GPLL_PLLOUT_ODD_SHFT = 2
-};
-
-enum clk_ctl_cfg_rcgr {
- CLK_CTL_CFG_HW_CTL_BMSK = 0x100000,
- CLK_CTL_CFG_HW_CTL_SHFT = 20,
- CLK_CTL_CFG_MODE_BMSK = 0x3000,
- CLK_CTL_CFG_MODE_SHFT = 12,
- CLK_CTL_CFG_SRC_SEL_BMSK = 0x700,
- CLK_CTL_CFG_SRC_SEL_SHFT = 8,
- CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F,
- CLK_CTL_CFG_SRC_DIV_SHFT = 0
-};
-
-enum clk_ctl_cmd_rcgr {
- CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000,
- CLK_CTL_CMD_ROOT_OFF_SHFT = 31,
- CLK_CTL_CMD_ROOT_EN_BMSK = 0x2,
- CLK_CTL_CMD_ROOT_EN_SHFT = 1,
- CLK_CTL_CMD_UPDATE_BMSK = 0x1,
- CLK_CTL_CMD_UPDATE_SHFT = 0
-};
-
-enum clk_ctl_cbcr {
- CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000,
- CLK_CTL_CBC_CLK_OFF_SHFT = 31,
- CLK_CTL_CBC_CLK_EN_BMSK = 0x1,
- CLK_CTL_CBC_CLK_EN_SHFT = 0
-};
-
-enum clk_ctl_rcg_mnd {
- CLK_CTL_RCG_MND_BMSK = 0xFFFF,
- CLK_CTL_RCG_MND_SHFT = 0,
-};
-
-enum clk_ctl_bcr {
- CLK_CTL_BCR_BLK_ARES_BMSK = 0x1,
- CLK_CTL_BCR_BLK_ARES_SHFT = 0,
-};
-
-enum clk_qup {
- QUP_WRAP0_S0,
- QUP_WRAP0_S1,
- QUP_WRAP0_S2,
- QUP_WRAP0_S3,
- QUP_WRAP0_S4,
- QUP_WRAP0_S5,
- QUP_WRAP0_S6,
- QUP_WRAP0_S7,
- QUP_WRAP1_S0,
- QUP_WRAP1_S1,
- QUP_WRAP1_S2,
- QUP_WRAP1_S3,
- QUP_WRAP1_S4,
- QUP_WRAP1_S5,
- QUP_WRAP1_S6,
- QUP_WRAP1_S7
-};
-
-struct clock_config {
- uint32_t hz;
- uint8_t src;
- uint8_t div;
- uint16_t m;
- uint16_t n;
- uint16_t d_2;
-};
-
-static struct sdm845_gcc *const gcc = (void *)GCC_BASE;
-
-void clock_init(void);
-void clock_reset_aop(void);
-void clock_configure_qspi(uint32_t hz);
-int clock_reset_bcr(void *bcr_addr, bool reset);
-void clock_configure_qup(int qup, uint32_t hz);
-void clock_enable_qup(int qup);
-
-#endif // __SOC_QUALCOMM_SDM845_CLOCK_H__
diff --git a/src/soc/qualcomm/sdm845/include/soc/efuse.h b/src/soc/qualcomm/sdm845/include/soc/efuse.h
deleted file mode 100644
index 112ffd3c20..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/efuse.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__
-#define __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__
-
-/**
- * USB EFUSE registers
- */
-struct qfprom_corr {
- u8 rsvd[0x41E8 - 0x0];
- u32 qusb_hstx_trim_lsb;
- u32 qusb_hstx_trim_msb;
-};
-
-check_member(qfprom_corr, qusb_hstx_trim_lsb, 0x41E8);
-check_member(qfprom_corr, qusb_hstx_trim_msb, 0x41EC);
-#endif /* __SOC_QUALCOMM_SDM845_EFUSE_ADDRESS_MAP_H__ */
diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h
deleted file mode 100644
index 04f92d6155..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/gpio.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_QUALCOMM_SDM845_GPIO_H_
-#define _SOC_QUALCOMM_SDM845_GPIO_H_
-
-#include <types.h>
-#include <soc/addressmap.h>
-
-typedef struct {
- u32 addr;
-} gpio_t;
-
-#define TLMM_TILE_SIZE 0x00400000
-#define TLMM_GPIO_OFF_DELTA 0x00001000
-#define TLMM_GPIO_TILE_NUM 3
-
-#define TLMM_GPIO_IN_OUT_OFF 0x4
-#define TLMM_GPIO_ID_STATUS_OFF 0x10
-
-#define GPIO_FUNC_ENABLE 1
-#define GPIO_FUNC_DISABLE 0
-
-/* GPIO TLMM: Direction */
-#define GPIO_INPUT 0
-#define GPIO_OUTPUT 1
-
-/* GPIO TLMM: Pullup/Pulldown */
-#define GPIO_NO_PULL 0
-#define GPIO_PULL_DOWN 1
-#define GPIO_KEEPER 2
-#define GPIO_PULL_UP 3
-
-/* GPIO TLMM: Drive Strength */
-#define GPIO_2MA 0
-#define GPIO_4MA 1
-#define GPIO_6MA 2
-#define GPIO_8MA 3
-#define GPIO_10MA 4
-#define GPIO_12MA 5
-#define GPIO_14MA 6
-#define GPIO_16MA 7
-
-/* GPIO TLMM: Status */
-#define GPIO_DISABLE 0
-#define GPIO_ENABLE 1
-
-/* GPIO TLMM: Mask */
-#define GPIO_CFG_PULL_BMSK 0x3
-#define GPIO_CFG_FUNC_BMSK 0xF
-#define GPIO_CFG_DRV_BMSK 0x7
-#define GPIO_CFG_OE_BMSK 0x1
-
-/* GPIO TLMM: Shift */
-#define GPIO_CFG_PULL_SHFT 0
-#define GPIO_CFG_FUNC_SHFT 2
-#define GPIO_CFG_DRV_SHFT 6
-#define GPIO_CFG_OE_SHFT 9
-
-/* GPIO IO: Mask */
-#define GPIO_IO_IN_BMSK 0x1
-#define GPIO_IO_OUT_BMSK 0x1
-
-/* GPIO IO: Shift */
-#define GPIO_IO_IN_SHFT 0
-#define GPIO_IO_OUT_SHFT 1
-
-/* GPIO ID STATUS: Mask */
-#define GPIO_ID_STATUS_BMSK 0x1
-
-/* GPIO MAX Valid # */
-#define GPIO_NUM_MAX 149
-
-#define GPIO_FUNC_GPIO 0
-
-#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR})
-
-#define PIN(index, tlmm, func1, func2, func3, func4, func5, func6, func7) \
-GPIO##index##_ADDR = TLMM_##tlmm##_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \
-GPIO##index##_FUNC_##func1 = 1, \
-GPIO##index##_FUNC_##func2 = 2, \
-GPIO##index##_FUNC_##func3 = 3, \
-GPIO##index##_FUNC_##func4 = 4, \
-GPIO##index##_FUNC_##func5 = 5, \
-GPIO##index##_FUNC_##func6 = 6, \
-GPIO##index##_FUNC_##func7 = 7
-
-enum {
- PIN(0, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(1, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(2, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(3, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(4, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(5, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(6, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(7, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(8, EAST, QUP_L4_0_CS, GP_PDM_MIRB, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(9, EAST, QUP_L5_0_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(10, EAST, MDP_VSYNC_P_MIRA, QUP_L6_0_CS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(11, EAST, MDP_VSYNC_S_MIRA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(12, SOUTH, MDP_VSYNC_E, RES_2, TSIF1_SYNC, RES_4, RES_5,
- RES_6, RES_7),
- PIN(13, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(14, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(15, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(16, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(17, SOUTH, CCI_I2C_SDA0, QUP_L0, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(18, SOUTH, CCI_I2C_SCL0, QUP_L1, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(19, SOUTH, CCI_I2C_SDA1, QUP_L2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(20, SOUTH, CCI_I2C_SCL1, QUP_L3, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(21, SOUTH, CCI_TIMER0, GCC_GP2_CLK_MIRB, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(22, SOUTH, CCI_TIMER1, GCC_GP3_CLK_MIRB, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(23, SOUTH, CCI_TIMER2, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(24, SOUTH, CCI_TIMER3, CCI_ASYNC_IN1, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(25, SOUTH, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(26, SOUTH, CCI_ASYNC_IN0, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(27, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(28, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(29, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(30, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(31, NORTH, QUP_L0, QUP_L2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(32, NORTH, QUP_L1, QUP_L3, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(33, NORTH, QUP_L2, QUP_L0, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(34, NORTH, QUP_L3, QUP_L1, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(35, SOUTH, PCI_E0_RST_N, QUP_L4_1_CS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(36, SOUTH, PCI_E0_CLKREQN, QUP_L5_1_CS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(37, SOUTH, QUP_L6_1_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(38, NORTH, USB_PHY_PS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(39, EAST, LPASS_SLIMBUS_DATA2, RES_2, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(40, SOUTH, SD_WRITE_PROTECT, TSIF1_ERROR, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(41, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(42, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(43, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(44, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(45, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(46, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(47, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(48, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(49, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(50, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(51, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(52, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(53, NORTH, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(54, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(55, NORTH, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(56, NORTH, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(57, NORTH, QUA_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(58, NORTH, QUA_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(59, NORTH, QUA_MI2S_WS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(60, NORTH, QUA_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(61, NORTH, QUA_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(62, NORTH, QUA_MI2S_DATA2, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(63, NORTH, QUA_MI2S_DATA3, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(64, NORTH, PRI_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(65, NORTH, PRI_MI2S_SCK, QUP_L0, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(66, NORTH, PRI_MI2S_WS, QUP_L1, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(67, NORTH, PRI_MI2S_DATA0, QUP_L2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(68, NORTH, PRI_MI2S_DATA1, QUP_L3, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(69, EAST, SPKR_I2S_MCLK, AUDIO_REF_CLK, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(70, EAST, LPASS_SLIMBUS_CLK, SPKR_I2S_SCK, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(71, EAST, LPASS_SLIMBUS_DATA0, SPKR_I2S_DATA_OUT, RES_3,
- RES_4, RES_5, RES_6, RES_7),
- PIN(72, EAST, LPASS_SLIMBUS_DATA1, SPKR_I2S_WS, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(73, EAST, BTFM_SLIMBUS_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(74, EAST, BTFM_SLIMBUS_CLK, TER_MI2S_MCLK, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(75, EAST, TER_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(76, EAST, TER_MI2S_WS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(77, EAST, TER_MI2S_DATA0, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(78, EAST, TER_MI2S_DATA1, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(79, NORTH, SEC_MI2S_MCLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(80, NORTH, SEC_MI2S_SCK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(81, NORTH, SEC_MI2S_WS, QUP_L0, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(82, NORTH, SEC_MI2S_DATA0, QUP_L1, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(83, NORTH, SEC_MI2S_DATA1, QUP_L2, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(84, NORTH, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(85, EAST, QUP_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(86, EAST, QUP_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(87, EAST, QUP_L2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(88, EAST, QUP_L3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(89, SOUTH, TSIF1_CLK, QUP_L0, QSPI_CS_N_1, RES_4, RES_5,
- RES_6, RES_7),
- PIN(90, SOUTH, TSIF1_EN, MDP_VSYNC0_OUT, QUP_L1, QSPI_CS_N_0,
- MDP_VSYNC1_OUT, MDP_VSYNC2_OUT, MDP_VSYNC3_OUT),
- PIN(91, SOUTH, TSIF1_DATA, SDC4_CMD, QUP_L2, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(92, SOUTH, TSIF2_ERROR, SDC4_DATA, QUP_L3, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(93, SOUTH, TSIF2_CLK, SDC4_CLK, QUP_L0, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(94, SOUTH, TSIF2_EN, SDC4_DATA, QUP_L1, QSPI_DATA,
- RES_5, RES_6, RES_7),
- PIN(95, SOUTH, TSIF2_DATA, SDC4_DATA, QUP_L2, QSPI_CLK,
- RES_5, RES_6, RES_7),
- PIN(96, SOUTH, TSIF2_SYNC, SDC4_DATA, QUP_L3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(97, NORTH, RFFE6_CLK, GRFC37, MDP_VSYNC_P_MIRB,
- RES_4, RES_5, RES_6, RES_7),
- PIN(98, NORTH, RFFE6_DATA, MDP_VSYNC_S_MIRB, RES_3,
- RES_4, RES_5, RES_6, RES_7),
- PIN(99, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(100, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(101, NORTH, GRFC4, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(102, NORTH, PCI_E1_RST_N, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(103, NORTH, PCI_E1_CLKREQN, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(104, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(105, NORTH, UIM2_DATA, QUP_L0, QUP_L4_8_CS, RES_4, RES_5,
- RES_6, RES_7),
- PIN(106, NORTH, UIM2_CLK, QUP_L1, QUP_L5_8_CS, RES_4, RES_5,
- RES_6, RES_7),
- PIN(107, NORTH, UIM2_RESET, QUP_L2, QUP_L6_8_CS, RES_4, RES_5,
- RES_6, RES_7),
- PIN(108, NORTH, UIM2_PRESENT, QUP_L3, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(109, NORTH, UIM1_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(110, NORTH, UIM1_CLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(111, NORTH, UIM1_RESET, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(112, NORTH, UIM1_PRESENT, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(113, NORTH, UIM_BATT_ALARM, EDP_HOT_PLUG_DETECT, RES_3,
- RES_4, RES_5, RES_6, RES_7),
- PIN(114, NORTH, GRFC8, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRE,
- RES_5, RES_6, RES_7),
- PIN(115, NORTH, GRFC9, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRF,
- RES_5, RES_6, RES_7),
- PIN(116, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(117, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(118, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(119, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(120, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(121, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(122, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(123, EAST, QUP_L4_9_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(124, EAST, QUP_L5_9_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(125, EAST, QUP_L6_9_CS, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(126, EAST, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(127, NORTH, GRFC3, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(128, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRB, RES_4,
- RES_5, RES_6, RES_7),
- PIN(129, NORTH, RES_1, RES_2, GPS_TX_AGGRESSOR_MIRC, RES_4,
- RES_5, RES_6, RES_7),
- PIN(130, NORTH, QLINK_REQUEST, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(131, NORTH, QLINK_ENABLE, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(132, NORTH, GRFC2, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(133, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(134, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(135, NORTH, GRFC0, PA_INDICATOR_1_OR_2, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(136, NORTH, GRFC1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(137, NORTH, RFFE3_DATA, GRFC35, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(138, NORTH, RFFE3_CLK, GRFC32, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(139, NORTH, RFFE4_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(140, NORTH, RFFE4_CLK, GRFC36, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(141, NORTH, RFFE5_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(142, NORTH, RFFE5_CLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(143, NORTH, GRFC5, RES_2, RES_3, GPS_TX_AGGRESSOR_MIRD,
- RES_5, RES_6, RES_7),
- PIN(144, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(145, NORTH, RES_1, GPS_TX_AGGRESSOR_MIRA, RES_3, RES_4,
- RES_5, RES_6, RES_7),
- PIN(146, NORTH, RFFE2_DATA, GRFC34, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(147, NORTH, RFFE2_CLK, GRFC33, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(148, NORTH, RFFE1_DATA, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
- PIN(149, NORTH, RFFE1_CLK, RES_2, RES_3, RES_4, RES_5,
- RES_6, RES_7),
-};
-
-struct tlmm_gpio {
- uint32_t cfg;
- uint32_t in_out;
-};
-
-void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull,
- uint32_t drive_str, uint32_t enable);
-
-#endif // _SOC_QUALCOMM_SDM845_GPIO_H_
diff --git a/src/soc/qualcomm/sdm845/include/soc/mmu.h b/src/soc/qualcomm/sdm845/include/soc/mmu.h
deleted file mode 100644
index 868a6c8105..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/mmu.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_QUALCOMM_SDM845_MMU_H__
-#define _SOC_QUALCOMM_SDM845_MMU_H__
-
-void sdm845_mmu_init(void);
-
-#endif // _SOC_QUALCOMM_SDM845_MMU_H_
diff --git a/src/soc/qualcomm/sdm845/include/soc/qspi.h b/src/soc/qualcomm/sdm845/include/soc/qspi.h
deleted file mode 100644
index 5357e48975..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/qspi.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#include <types.h>
-#include <soc/addressmap.h>
-#include <spi-generic.h>
-
-#ifndef __SOC_QUALCOMM_SDM845_QSPI_H__
-#define __SOC_QUALCOMM_SDM845_QSPI_H__
-
-struct sdm845_qspi_regs {
- u32 mstr_cfg;
- u32 ahb_mstr_cfg;
- u32 reserve_0;
- u32 mstr_int_en;
- u32 mstr_int_sts;
- u32 pio_xfer_ctrl;
- u32 pio_xfer_cfg;
- u32 pio_xfer_sts;
- u32 pio_dataout_1byte;
- u32 pio_dataout_4byte;
- u32 rd_fifo_cfg;
- u32 rd_fifo_sts;
- u32 rd_fifo_rst;
- u32 reserve_1[3];
- u32 next_dma_desc_addr;
- u32 current_dma_desc_addr;
- u32 current_mem_addr;
- u32 hw_version;
- u32 rd_fifo[16];
-};
-
-check_member(sdm845_qspi_regs, rd_fifo, 0x50);
-static struct sdm845_qspi_regs * const sdm845_qspi = (void *) QSPI_BASE;
-
-// MSTR_CONFIG register
-
-#define TX_DATA_OE_DELAY_SHIFT 24
-#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT)
-#define TX_CS_N_DELAY_SHIFT 22
-#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT)
-#define TX_CLK_DELAY_SHIFT 20
-#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT)
-#define TX_DATA_DELAY_SHIFT 18
-#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT)
-#define LPA_BASE_SHIFT 14
-#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT)
-#define SBL_EN BIT(13)
-#define CHIP_SELECT_NUM BIT(12)
-#define SPI_MODE_SHIFT 10
-#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT)
-#define BIG_ENDIAN_MODE BIT(9)
-#define DMA_ENABLE BIT(8)
-#define PIN_WPN BIT(7)
-#define PIN_HOLDN BIT(6)
-#define FB_CLK_EN BIT(4)
-#define FULL_CYCLE_MODE BIT(3)
-
-// MSTR_INT_ENABLE and MSTR_INT_STATUS register
-
-#define DMA_CHAIN_DONE BIT(31)
-#define TRANSACTION_DONE BIT(16)
-#define WRITE_FIFO_OVERRUN BIT(11)
-#define WRITE_FIFO_FULL BIT(10)
-#define HRESP_FROM_NOC_ERR BIT(3)
-#define RESP_FIFO_RDY BIT(2)
-#define RESP_FIFO_NOT_EMPTY BIT(1)
-#define RESP_FIFO_UNDERRUN BIT(0)
-
-// PIO_TRANSFER_CONFIG register
-
-#define TRANSFER_FRAGMENT BIT(8)
-#define MULTI_IO_MODE_SHIFT 1
-#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT)
-#define TRANSFER_DIRECTION BIT(0)
-
-// PIO_TRANSFER_STATUS register
-
-#define WR_FIFO_BYTES_SHIFT 16
-#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT)
-
-// RD_FIFO_CONFIG register
-
-#define CONTINUOUS_MODE BIT(0)
-
-// RD_FIFO_STATUS register
-
-#define FIFO_EMPTY BIT(11)
-#define WR_CNTS_SHIFT 4
-#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT)
-#define RDY_64BYTE BIT(3)
-#define RDY_32BYTE BIT(2)
-#define RDY_16BYTE BIT(1)
-#define FIFO_RDY BIT(0)
-
-// RD_FIFO_RESET register
-
-#define RESET_FIFO BIT(0)
-
-#define QSPI_MAX_PACKET_COUNT 0xFFC0
-
-void quadspi_init(uint32_t hz);
-int sdm845_claim_bus(const struct spi_slave *slave);
-int sdm845_setup_bus(const struct spi_slave *slave);
-void sdm845_release_bus(const struct spi_slave *slave);
-int sdm845_xfer(const struct spi_slave *slave, const void *dout,
- size_t out_bytes, void *din, size_t in_bytes);
-int sdm845_xfer_dual(const struct spi_slave *slave, const void *dout,
- size_t out_bytes, void *din, size_t in_bytes);
-#endif /* __SOC_QUALCOMM_SDM845_QSPI_H__ */
diff --git a/src/soc/qualcomm/sdm845/include/soc/symbols.h b/src/soc/qualcomm/sdm845/include/soc/symbols.h
deleted file mode 100644
index 64482c73d2..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/symbols.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _SOC_QUALCOMM_SDM845_SYMBOLS_H_
-#define _SOC_QUALCOMM_SDM845_SYMBOLS_H_
-
-#include <symbols.h>
-
-DECLARE_REGION(ssram)
-DECLARE_REGION(bsram)
-DECLARE_REGION(dram_reserved)
-DECLARE_REGION(dcb);
-DECLARE_REGION(pmic);
-DECLARE_REGION(limits_cfg);
-DECLARE_REGION(aop);
-DECLARE_REGION(aop_ss_msg_ram_drv15);
-
-#endif // _SOC_QUALCOMM_SDM845_SYMBOLS_H_
diff --git a/src/soc/qualcomm/sdm845/include/soc/usb.h b/src/soc/qualcomm/sdm845/include/soc/usb.h
deleted file mode 100644
index 5ce8f805ca..0000000000
--- a/src/soc/qualcomm/sdm845/include/soc/usb.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-#include <types.h>
-
-#ifndef _SDM845_USB_H_
-#define _SDM845_USB_H_
-
-/* QSCRATCH_GENERAL_CFG register bit offset */
-#define PIPE_UTMI_CLK_SEL BIT(0)
-#define PIPE3_PHYSTATUS_SW BIT(3)
-#define PIPE_UTMI_CLK_DIS BIT(8)
-
-/* Global USB3 Control Registers */
-#define DWC3_GUSB3PIPECTL_DELAYP1TRANS BIT(18)
-#define DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX BIT(27)
-#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
-#define DWC3_GCTL_PRTCAP_OTG 3
-#define DWC3_GCTL_PRTCAP_HOST 1
-
-/* Global USB2 PHY Configuration Register */
-#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) ((n) << 10)
-#define DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
-#define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3)
-#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
-#define USBTRDTIM_UTMI_8_BIT 9
-#define UTMI_PHYIF_8_BIT 0
-
-#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
-#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
-#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
-#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
-#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
-
-#define PORT_TUNE1_MASK 0xf0
-
-/* QUSB2PHY_PWR_CTRL1 register related bits */
-#define POWER_DOWN BIT(0)
-
-/* DEBUG_CTRL2 register value to program VSTATUS MUX for PHY status */
-#define DEBUG_CTRL2_MUX_PLL_LOCK_STATUS 0x4
-
-/* STAT5 register bits */
-#define VSTATUS_PLL_LOCK_STATUS_MASK BIT(0)
-
-/* QUSB PHY register values */
-#define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x03
-#define QUSB2PHY_PLL_CLOCK_INVERTERS 0x7c
-#define QUSB2PHY_PLL_CMODE 0x80
-#define QUSB2PHY_PLL_LOCK_DELAY 0x0a
-#define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0x19
-#define QUSB2PHY_PLL_BIAS_CONTROL_1 0x40
-#define QUSB2PHY_PLL_BIAS_CONTROL_2 0x20
-#define QUSB2PHY_PWR_CTRL2 0x21
-#define QUSB2PHY_IMP_CTRL1 0x0
-#define QUSB2PHY_IMP_CTRL2 0x58
-#define QUSB2PHY_PORT_TUNE1 0x30
-#define QUSB2PHY_PORT_TUNE2 0x29
-#define QUSB2PHY_PORT_TUNE3 0xca
-#define QUSB2PHY_PORT_TUNE4 0x04
-#define QUSB2PHY_PORT_TUNE5 0x03
-#define QUSB2PHY_CHG_CTRL2 0x0
-
-/* USB3PHY_PCIE_USB3_PCS_PCS_STATUS bit */
-#define USB3_PCS_PHYSTATUS BIT(6)
-
-struct usb_board_data {
- /* Register values going to override from the boardfile */
- u32 pll_bias_control_2;
- u32 imp_ctrl1;
- u32 port_tune1;
-};
-
-struct qmp_phy_init_tbl {
- u32 *address;
- u32 val;
-};
-
-void setup_usb_host0(struct usb_board_data *data);
-void setup_usb_host1(struct usb_board_data *data);
-/* Call reset_ before setup_ */
-void reset_usb0(void);
-void reset_usb1(void);
-
-#endif /* _SDM845_USB_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 07:24:23 +0000