diff options
Diffstat (limited to 'src/soc/qualcomm/common')
| -rw-r--r-- | src/soc/qualcomm/common/clock.c | 23 | ||||
| -rw-r--r-- | src/soc/qualcomm/common/include/soc/clock_common.h | 2 |
2 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/qualcomm/common/clock.c b/src/soc/qualcomm/common/clock.c index e83f979e81..09cd95c88a 100644 --- a/src/soc/qualcomm/common/clock.c +++ b/src/soc/qualcomm/common/clock.c @@ -236,6 +236,29 @@ enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg) return CB_SUCCESS; } +enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg) +{ + setbits32(cfg->reg_mode, BIT(PLL_BYPASSNL_SHFT)); + + /* + * H/W requires a 1us delay between disabling the bypass and + * de-asserting the reset. + */ + udelay(1); + setbits32(cfg->reg_mode, BIT(PLL_RESET_SHFT)); + setbits32(cfg->reg_opmode, PLL_RUN_MODE); + + if (!wait_us(100, read32(cfg->reg_mode) & PLL_LOCK_DET_BMSK)) { + printk(BIOS_ERR, "ERROR: CPU PLL did not lock!\n"); + return CB_ERR; + } + + setbits32(cfg->reg_user_ctl, PLL_USERCTL_BMSK); + setbits32(cfg->reg_mode, BIT(PLL_OUTCTRL_SHFT)); + + return CB_SUCCESS; +} + /* Bring subsystem out of RESET */ void clock_reset_subsystem(u32 *misc, u32 shft) { diff --git a/src/soc/qualcomm/common/include/soc/clock_common.h b/src/soc/qualcomm/common/include/soc/clock_common.h index b9241944c2..0911827149 100644 --- a/src/soc/qualcomm/common/include/soc/clock_common.h +++ b/src/soc/qualcomm/common/include/soc/clock_common.h @@ -155,6 +155,8 @@ enum cb_err clock_configure_enable_gpll(struct alpha_pll_reg_val_config *cfg, bool enable, int br_enable); enum cb_err agera_pll_enable(struct alpha_pll_reg_val_config *cfg); +enum cb_err zonda_pll_enable(struct alpha_pll_reg_val_config *cfg); + struct aoss { u8 _res0[0x50020]; u32 aoss_cc_reset_status; |