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-rw-r--r--src/soc/nvidia/tegra124/clock.c107
-rw-r--r--src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c87
-rw-r--r--src/soc/nvidia/tegra124/power.c6
-rw-r--r--src/soc/nvidia/tegra124/spi.c22
-rw-r--r--src/soc/nvidia/tegra124/uart.c19
5 files changed, 100 insertions, 141 deletions
diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c
index 225a764431..dc1d1dbe8a 100644
--- a/src/soc/nvidia/tegra124/clock.c
+++ b/src/soc/nvidia/tegra124/clock.c
@@ -186,11 +186,11 @@ void clock_init_arm_generic_timer(void)
set_cntfrq(freq);
// Record the system timer frequency.
- write32(freq, &sysctr->cntfid0);
+ writel(freq, &sysctr->cntfid0);
// Enable the system counter.
uint32_t cntcr = read32(&sysctr->cntcr);
cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG;
- write32(cntcr, &sysctr->cntcr);
+ writel(cntcr, &sysctr->cntcr);
}
#define SOR0_CLK_SEL0 (1 << 14)
@@ -243,25 +243,14 @@ static void init_utmip_pll(void)
clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
udelay(1);
- write32(80 << 16 | /* (rst) phy_divn */
- 1 << 8 | /* (rst) phy_divm */
- 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */
+ writel(80 << 16 | 1 << 8 | 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */
- write32(CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */
- 0 << 16 | /* PLLU pwrdn */
- 0 << 14 | /* pll_enable pwrdn */
- 0 << 12 | /* pll_active pwrdn */
- CEIL_DIV(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */
- 0, &clk_rst->utmip_pll_cfg1);
+ writel(CEIL_DIV(khz, 8000) << 27 | 0 << 16 | 0 << 14 | 0 << 12 | CEIL_DIV(khz, 102) << 0 | 0,
+ &clk_rst->utmip_pll_cfg1);
/* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */
- write32(0 << 24 | /* SAMP_D/XDEV pwrdn */
- CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */
- CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */
- 0 << 4 | /* SAMP_C/USB3 pwrdn */
- 0 << 2 | /* SAMP_B/XHOST pwrdn */
- 0 << 0 | /* SAMP_A/USBD pwrdn */
- 0, &clk_rst->utmip_pll_cfg2);
+ writel(0 << 24 | CEIL_DIV(khz, 3200) << 18 | CEIL_DIV(khz, 256) << 6 | 0 << 4 | 0 << 2 | 0 << 0 | 0,
+ &clk_rst->utmip_pll_cfg2);
setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */
}
@@ -398,8 +387,8 @@ clock_display(u32 frequency)
* been determined through trial and error (must lead to div 13 at 24MHz). */
void clock_early_uart(void)
{
- write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE |
- CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900), &clk_rst->clk_src_uarta);
+ writel(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1900),
+ &clk_rst->clk_src_uarta);
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA);
udelay(2);
clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA);
@@ -486,28 +475,24 @@ void clock_cpu0_config(void *entry)
{
void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100;
- write32((uintptr_t)_estack, &maincpu_stack_pointer);
- write32((uintptr_t)entry, &maincpu_entry_point);
- write32((uintptr_t)&maincpu_setup, evp_cpu_reset);
+ writel((uintptr_t)_estack, &maincpu_stack_pointer);
+ writel((uintptr_t)entry, &maincpu_entry_point);
+ writel((uintptr_t)&maincpu_setup, evp_cpu_reset);
/* Set active CPU cluster to G */
clrbits_le32(&flow->cluster_control, 1);
// Set up cclk_brst and divider.
- write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) |
- (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) |
- (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) |
- (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) |
- (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28),
- &clk_rst->cclk_brst_pol);
- write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
- &clk_rst->super_cclk_div);
+ writel((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28),
+ &clk_rst->cclk_brst_pol);
+ writel(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB,
+ &clk_rst->super_cclk_div);
// Enable the clocks for CPUs 0-3.
uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr);
cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP |
CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP;
- write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
+ writel(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr);
// Enable other CPU related clocks.
setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU);
@@ -518,36 +503,23 @@ void clock_cpu0_config(void *entry)
void clock_cpu0_remove_reset(void)
{
// Disable the reset on the non-CPU parts of the fast cluster.
- write32(CRC_RST_CPUG_CLR_NONCPU,
- &clk_rst->rst_cpug_cmplx_clr);
+ writel(CRC_RST_CPUG_CLR_NONCPU, &clk_rst->rst_cpug_cmplx_clr);
// Disable the various resets on the CPUs.
- write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 |
- CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 |
- CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 |
- CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 |
- CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 |
- CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 |
- CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 |
- CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 |
- CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
- &clk_rst->rst_cpug_cmplx_clr);
+ writel(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG,
+ &clk_rst->rst_cpug_cmplx_clr);
// Disable the reset on the non-CPU parts of the slow cluster.
- write32(CRC_RST_CPULP_CLR_NONCPU,
- &clk_rst->rst_cpulp_cmplx_clr);
+ writel(CRC_RST_CPULP_CLR_NONCPU, &clk_rst->rst_cpulp_cmplx_clr);
// Disable the various resets on the LP CPU.
- write32(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 |
- CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 |
- CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
- &clk_rst->rst_cpulp_cmplx_clr);
+ writel(CRC_RST_CPULP_CLR_CPU0 | CRC_RST_CPULP_CLR_DBG0 | CRC_RST_CPULP_CLR_CORE0 | CRC_RST_CPULP_CLR_CX0 | CRC_RST_CPULP_CLR_L2 | CRC_RST_CPULP_CLR_PDBG,
+ &clk_rst->rst_cpulp_cmplx_clr);
}
void clock_halt_avp(void)
{
for (;;) {
- write32(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ |
- FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
- &flow->halt_cop_events);
+ writel(FLOW_EVENT_JTAG | FLOW_EVENT_LIC_IRQ | FLOW_EVENT_GIC_IRQ | FLOW_MODE_WAITEVENT,
+ &flow->halt_cop_events);
}
}
@@ -564,15 +536,12 @@ void clock_init(void)
/* Typical ratios are 1:2:2 or 1:2:3 sclk:hclk:pclk (See: APB DMA
* features section in the TRM). */
- write32(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT |
- TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT,
- &clk_rst->clk_sys_rate);
- write32(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) <<
- PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN |
- PLL_OUT_RSTN, &clk_rst->pllc_out);
- write32(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT |
- SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
- &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */
+ writel(TEGRA_HCLK_RATIO << HCLK_DIVISOR_SHIFT | TEGRA_PCLK_RATIO << PCLK_DIVISOR_SHIFT,
+ &clk_rst->clk_sys_rate);
+ writel(CLK_DIVIDER(TEGRA_PLLC_KHZ, TEGRA_SCLK_KHZ) << PLL_OUT_RATIO_SHIFT | PLL_OUT_CLKEN | PLL_OUT_RSTN,
+ &clk_rst->pllc_out);
+ writel(SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT | SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT,
+ &clk_rst->sclk_brst_pol); /* sclk = 300 MHz */
/* Change the oscillator drive strength (from U-Boot -- why?) */
clrsetbits_le32(&clk_rst->osc_ctrl, OSC_XOFS_MASK,
@@ -590,16 +559,10 @@ void clock_init(void)
clrbits_le32(&clk_rst->pllx_misc3, PLLX_IDDQ_MASK);
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
- write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT |
- (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
- &clk_rst->pllp_outa);
- write32((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT |
- (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT |
- PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
- &clk_rst->pllp_outb);
+ writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 9600) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT1_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 48000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT2_SHIFT,
+ &clk_rst->pllp_outa);
+ writel((CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT3_SHIFT | (CLK_DIVIDER(TEGRA_PLLP_KHZ, 204000) << PLL_OUT_RATIO_SHIFT | PLL_OUT_OVR | PLL_OUT_CLKEN | PLL_OUT_RSTN) << PLL_OUT4_SHIFT,
+ &clk_rst->pllp_outb);
/* init pllx */
init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc,
diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
index 0a3cb48641..9418e152da 100644
--- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
+++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c
@@ -282,17 +282,17 @@ inline static void write32(uint32_t val, void *addr)
inline static void setbits32(uint32_t bits, void *addr)
{
- write32(read32(addr) | bits, addr);
+ writel(read32(addr) | bits, addr);
}
inline static void clrbits32(uint32_t bits, void *addr)
{
- write32(read32(addr) & ~bits, addr);
+ writel(read32(addr) & ~bits, addr);
}
static void __attribute__((noreturn)) reset(void)
{
- write32(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
+ writel(SWR_TRIG_SYS_RST, clk_rst_rst_devices_l_ptr);
halt();
}
@@ -337,7 +337,7 @@ static void config_oscillator(void)
osc_ctrl &= ~OSC_XOFS_MASK;
osc_ctrl |= (xofs << OSC_XOFS_SHIFT);
osc_ctrl |= OSC_XOE;
- write32(osc_ctrl, clk_rst_osc_ctrl_ptr);
+ writel(osc_ctrl, clk_rst_osc_ctrl_ptr);
}
static void config_pllu(void)
@@ -382,17 +382,17 @@ static void config_pllu(void)
// Configure PLLU.
uint32_t base = PLLU_BYPASS | PLLU_OVERRIDE |
(divn << PLLU_DIVN_SHIFT) | (divm << PLLU_DIVM_SHIFT);
- write32(base, clk_rst_pllu_base_ptr);
+ writel(base, clk_rst_pllu_base_ptr);
uint32_t misc = (cpcon << PLLU_CPCON_SHIFT) |
(lfcon << PLLU_LFCON_SHIFT);
- write32(misc, clk_rst_pllu_misc_ptr);
+ writel(misc, clk_rst_pllu_misc_ptr);
// Enable PLLU.
base &= ~PLLU_BYPASS;
base |= PLLU_ENABLE;
- write32(base, clk_rst_pllu_base_ptr);
+ writel(base, clk_rst_pllu_base_ptr);
misc |= PLLU_LOCK_ENABLE;
- write32(misc, clk_rst_pllu_misc_ptr);
+ writel(misc, clk_rst_pllu_misc_ptr);
}
static void config_tsc(void)
@@ -400,26 +400,26 @@ static void config_tsc(void)
// Tell the TSC the oscillator frequency.
switch (get_osc_freq()) {
case OSC_FREQ_12:
- write32(12000000, sysctr_cntfid0_ptr);
+ writel(12000000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_48:
- write32(48000000, sysctr_cntfid0_ptr);
+ writel(48000000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_16P8:
- write32(16800000, sysctr_cntfid0_ptr);
+ writel(16800000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_19P2:
- write32(19200000, sysctr_cntfid0_ptr);
+ writel(19200000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_38P4:
- write32(38400000, sysctr_cntfid0_ptr);
+ writel(38400000, sysctr_cntfid0_ptr);
break;
case OSC_FREQ_26:
- write32(26000000, sysctr_cntfid0_ptr);
+ writel(26000000, sysctr_cntfid0_ptr);
break;
default:
// Default to 13MHz.
- write32(13000000, sysctr_cntfid0_ptr);
+ writel(13000000, sysctr_cntfid0_ptr);
break;
}
@@ -430,8 +430,8 @@ static void config_tsc(void)
static void enable_cpu_clocks(void)
{
// Enable the CPU complex clock.
- write32(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
- write32(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
+ writel(CLK_ENB_CPU, clk_rst_clk_enb_l_set_ptr);
+ writel(CLK_ENB_CPUG | CLK_ENB_CPULP, clk_rst_clk_enb_v_set_ptr);
}
@@ -441,7 +441,7 @@ static void enable_cpu_clocks(void)
static void config_core_sight(void)
{
// Enable the CoreSight clock.
- write32(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
+ writel(CLK_ENB_CSITE, clk_rst_clk_out_enb_u_set_ptr);
/*
* De-assert CoreSight reset.
@@ -449,22 +449,22 @@ static void config_core_sight(void)
* now. It will be restored to its original clock source
* when the CPU-side restoration code runs.
*/
- write32(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
+ writel(SWR_CSITE_RST, clk_rst_rst_dev_u_clr_ptr);
}
static void config_mselect(void)
{
// Set MSELECT clock source to PLLP with 1:4 divider.
- write32((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0,
- clk_rst_clk_src_mselect_ptr);
+ writel((6 << MSELECT_CLK_DIV_SHIFT) | MSELECT_CLK_SRC_PLLP_OUT0,
+ clk_rst_clk_src_mselect_ptr);
// Enable clock to MSELECT.
- write32(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr);
+ writel(CLK_ENB_MSELECT, clk_rst_clk_enb_v_set_ptr);
udelay(2);
// Bring MSELECT out of reset.
- write32(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr);
+ writel(SWR_MSELECT_RST, clk_rst_rst_dev_v_clr_ptr);
}
@@ -474,19 +474,16 @@ static void config_mselect(void)
static void clear_cpu_resets(void)
{
// Take the non-cpu of the G and LP clusters out of reset.
- write32(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr);
- write32(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr);
+ writel(CLR_NONCPURESET, clk_rst_rst_cpulp_cmplx_clr_ptr);
+ writel(CLR_NONCPURESET, clk_rst_rst_cpug_cmplx_clr_ptr);
// Clear software controlled reset of the slow cluster.
- write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
- clk_rst_rst_cpulp_cmplx_clr_ptr);
+ writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0,
+ clk_rst_rst_cpulp_cmplx_clr_ptr);
// Clear software controlled reset of the fast cluster.
- write32(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 |
- CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 |
- CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 |
- CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3,
- clk_rst_rst_cpug_cmplx_clr_ptr);
+ writel(CLR_CPURESET0 | CLR_DBGRESET0 | CLR_CORERESET0 | CLR_CXRESET0 | CLR_CPURESET1 | CLR_DBGRESET1 | CLR_CORERESET1 | CLR_CXRESET1 | CLR_CPURESET2 | CLR_DBGRESET2 | CLR_CORERESET2 | CLR_CXRESET2 | CLR_CPURESET3 | CLR_DBGRESET3 | CLR_CORERESET3 | CLR_CXRESET3,
+ clk_rst_rst_cpug_cmplx_clr_ptr);
}
@@ -516,7 +513,7 @@ static void power_on_partition(unsigned id)
uint32_t bit = 0x1 << id;
if (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit)) {
// Partition is not on. Turn it on.
- write32(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
+ writel(id | PWRGATE_TOGGLE_START, pmc_ctlr_pwrgate_toggle_ptr);
// Wait until the partition is powerd on.
while (!(read32(pmc_ctlr_pwrgate_status_ptr) & bit))
@@ -546,8 +543,8 @@ static void power_on_main_cpu(void)
*/
uint32_t orig_timer = read32(pmc_ctlr_cpupwrgood_timer_ptr);
- write32(orig_timer * (204000000 / 32768),
- pmc_ctlr_cpupwrgood_timer_ptr);
+ writel(orig_timer * (204000000 / 32768),
+ pmc_ctlr_cpupwrgood_timer_ptr);
if (wakeup_on_lp()) {
power_on_partition(PARTID_C1NC);
@@ -559,7 +556,7 @@ static void power_on_main_cpu(void)
}
// Restore the original PMC_CPUPWRGOOD_TIMER.
- write32(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
+ writel(orig_timer, pmc_ctlr_cpupwrgood_timer_ptr);
}
@@ -581,17 +578,17 @@ void lp0_resume(void)
flow_ctlr_cluster_control_ptr);
// Program SUPER_CCLK_DIVIDER.
- write32(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
+ writel(SUPER_CDIV_ENB, clk_rst_super_cclk_div_ptr);
config_core_sight();
config_pllu();
// Set the CPU reset vector.
- write32(get_wakeup_vector(), evp_cpu_reset_ptr);
+ writel(get_wakeup_vector(), evp_cpu_reset_ptr);
// Select CPU complex clock source.
- write32(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
+ writel(CCLK_PLLP_BURST_POLICY, clk_rst_cclk_burst_policy_ptr);
config_mselect();
@@ -602,14 +599,14 @@ void lp0_resume(void)
uint32_t ack_width = read32(clk_rst_cpu_softrst_ctrl2_ptr);
ack_width &= ~CAR2PMC_CPU_ACK_WIDTH_MASK;
ack_width |= 408 << CAR2PMC_CPU_ACK_WIDTH_SHIFT;
- write32(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
+ writel(ack_width, clk_rst_cpu_softrst_ctrl2_ptr);
config_tsc();
// Disable VPR.
- write32(0, mc_video_protect_size_mb_ptr);
- write32(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
- mc_video_protect_reg_ctrl_ptr);
+ writel(0, mc_video_protect_size_mb_ptr);
+ writel(VIDEO_PROTECT_WRITE_ACCESS_DISABLE,
+ mc_video_protect_reg_ctrl_ptr);
enable_cpu_clocks();
@@ -622,8 +619,8 @@ void lp0_resume(void)
// Halt the AVP.
while (1)
- write32(FLOW_MODE_STOP | EVENT_JTAG,
- flow_ctlr_halt_cop_events_ptr);
+ writel(FLOW_MODE_STOP | EVENT_JTAG,
+ flow_ctlr_halt_cop_events_ptr);
}
diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c
index 825b27bda9..b31d3a7781 100644
--- a/src/soc/nvidia/tegra124/power.c
+++ b/src/soc/nvidia/tegra124/power.c
@@ -48,7 +48,7 @@ static void power_ungate_partition(uint32_t id)
pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK);
pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT);
pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START;
- write32(pwrgate_toggle, &pmc->pwrgate_toggle);
+ writel(pwrgate_toggle, &pmc->pwrgate_toggle);
// Wait for the request to be accepted.
while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START)
@@ -73,12 +73,12 @@ void power_enable_and_ungate_cpu(void)
* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (150MHz),
* set it for 5ms as per SysEng (5ms * PCLK_KHZ * 1000 / 1s).
*/
- write32((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer);
+ writel((TEGRA_PCLK_KHZ * 5), &pmc->cpupwrgood_timer);
uint32_t cntrl = read32(&pmc->cntrl);
cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY;
cntrl |= PMC_CNTRL_CPUPWRREQ_OE;
- write32(cntrl, &pmc->cntrl);
+ writel(cntrl, &pmc->cntrl);
power_ungate_partition(POWER_PARTID_CRAIL);
diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c
index aefb4da0d6..0584177d5e 100644
--- a/src/soc/nvidia/tegra124/spi.c
+++ b/src/soc/nvidia/tegra124/spi.c
@@ -230,7 +230,7 @@ int spi_claim_bus(struct spi_slave *slave)
else
val |= SPI_CMD1_CS_SW_VAL;
- write32(val, &regs->command1);
+ writel(val, &regs->command1);
return 0;
}
@@ -246,7 +246,7 @@ void spi_release_bus(struct spi_slave *slave)
else
val &= ~SPI_CMD1_CS_SW_VAL;
- write32(val, &regs->command1);
+ writel(val, &regs->command1);
}
static void dump_fifo_status(struct tegra_spi_channel *spi)
@@ -383,12 +383,12 @@ static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi,
/* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and
* PIO transfers */
- write32(todo - 1, &spi->regs->dma_blk);
+ writel(todo - 1, &spi->regs->dma_blk);
if (dir == SPI_SEND) {
unsigned int to_fifo = bytes;
while (to_fifo) {
- write32(*p, &spi->regs->tx_fifo);
+ writel(*p, &spi->regs->tx_fifo);
p++;
to_fifo--;
}
@@ -493,11 +493,11 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* ensure bytes to send will be visible to DMA controller */
dcache_clean_by_mva(spi->out_buf, bytes);
- write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
- write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
+ writel((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr);
+ writel((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr);
setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out);
- write32(wcount, &spi->dma_out->regs->wcount);
+ writel(wcount, &spi->dma_out->regs->wcount);
} else {
spi->dma_in = dma_claim();
if (!spi->dma_in)
@@ -506,15 +506,15 @@ static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi,
/* avoid data collisions */
dcache_clean_invalidate_by_mva(spi->in_buf, bytes);
- write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
- write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
+ writel((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr);
+ writel((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr);
clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_in);
- write32(wcount, &spi->dma_in->regs->wcount);
+ writel(wcount, &spi->dma_in->regs->wcount);
}
/* BLOCK_SIZE starts at n-1 */
- write32(todo - 1, &spi->regs->dma_blk);
+ writel(todo - 1, &spi->regs->dma_blk);
return todo;
}
diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c
index a25540b025..26aec20030 100644
--- a/src/soc/nvidia/tegra124/uart.c
+++ b/src/soc/nvidia/tegra124/uart.c
@@ -56,20 +56,19 @@ static void tegra124_uart_init(struct tegra124_uart *uart_ptr)
tegra124_uart_tx_flush(uart_ptr);
// Disable interrupts.
- write8(0, &uart_ptr->ier);
+ writeb(0, &uart_ptr->ier);
// Force DTR and RTS to high.
- write8(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+ writeb(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
// Set line configuration, access divisor latches.
- write8(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+ writeb(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
// Set the divisor.
- write8(divisor & 0xff, &uart_ptr->dll);
- write8((divisor >> 8) & 0xff, &uart_ptr->dlm);
+ writeb(divisor & 0xff, &uart_ptr->dll);
+ writeb((divisor >> 8) & 0xff, &uart_ptr->dlm);
// Hide the divisor latches.
- write8(line_config, &uart_ptr->lcr);
+ writeb(line_config, &uart_ptr->lcr);
// Enable FIFOs, and clear receive and transmit.
- write8(UART8250_FCR_FIFO_EN |
- UART8250_FCR_CLEAR_RCVR |
- UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+ writeb(UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR | UART8250_FCR_CLEAR_XMIT,
+ &uart_ptr->fcr);
}
static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
@@ -82,7 +81,7 @@ static unsigned char tegra124_uart_rx_byte(struct tegra124_uart *uart_ptr)
static void tegra124_uart_tx_byte(struct tegra124_uart *uart_ptr, unsigned char data)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
- write8(data, &uart_ptr->thr);
+ writeb(data, &uart_ptr->thr);
}
static void tegra124_uart_tx_flush(struct tegra124_uart *uart_ptr)
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 21:29:51 +0000