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-rw-r--r--src/soc/mediatek/common/include/soc/dsi_common.h45
-rw-r--r--src/soc/mediatek/common/include/soc/dsi_register_v1.h56
-rw-r--r--src/soc/mediatek/common/include/soc/dsi_register_v2.h56
-rw-r--r--src/soc/mediatek/mt8173/include/soc/dsi.h1
-rw-r--r--src/soc/mediatek/mt8183/include/soc/dsi.h1
-rw-r--r--src/soc/mediatek/mt8186/include/soc/dsi.h1
-rw-r--r--src/soc/mediatek/mt8192/include/soc/dsi.h1
7 files changed, 116 insertions, 45 deletions
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index bc4bfa17a6..a0acce829b 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -45,53 +45,8 @@ enum {
MIPI_DSI_MODE_LINE_END = BIT(12),
};
-struct dsi_regs {
- u32 dsi_start;
- u8 reserved0[4];
- u32 dsi_inten;
- u32 dsi_intsta;
- u32 dsi_con_ctrl;
- u32 dsi_mode_ctrl;
- u32 dsi_txrx_ctrl;
- u32 dsi_psctrl;
- u32 dsi_vsa_nl;
- u32 dsi_vbp_nl;
- u32 dsi_vfp_nl;
- u32 dsi_vact_nl;
- u32 dsi_lfr_con; /* Available since MT8183 */
- u32 dsi_lfr_sta; /* Available since MT8183 */
- u32 dsi_size_con; /* Available since MT8183 */
- u32 dsi_vfp_early_stop; /* Available since MT8183 */
- u32 reserved1[4];
- u32 dsi_hsa_wc;
- u32 dsi_hbp_wc;
- u32 dsi_hfp_wc;
- u32 dsi_bllp_wc;
- u32 dsi_cmdq_size;
- u32 dsi_hstx_cklp_wc;
- u8 reserved2[156];
- u32 dsi_phy_lccon;
- u32 dsi_phy_ld0con;
- u8 reserved3[4];
- u32 dsi_phy_timecon0;
- u32 dsi_phy_timecon1;
- u32 dsi_phy_timecon2;
- u32 dsi_phy_timecon3;
- u8 reserved4[16];
- u32 dsi_vm_cmd_con;
- u8 reserved5[92];
- u32 dsi_force_commit; /* Available since MT8183 */
- u8 reserved6[108];
- u32 dsi_cmdq[128];
-};
static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
-check_member(dsi_regs, dsi_phy_lccon, 0x104);
-check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
-check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
-check_member(dsi_regs, dsi_force_commit, 0x190);
-check_member(dsi_regs, dsi_cmdq, 0x200);
-
/* DSI_INTSTA */
enum {
LPRX_RD_RDY_INT_FLAG = BIT(0),
diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v1.h b/src/soc/mediatek/common/include/soc/dsi_register_v1.h
new file mode 100644
index 0000000000..ec5dfdac63
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dsi_register_v1.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DSI_REGISTER_V1_H
+#define DSI_REGISTER_V1_H
+
+#include <commonlib/helpers.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct dsi_regs {
+ u32 dsi_start;
+ u8 reserved0[4];
+ u32 dsi_inten;
+ u32 dsi_intsta;
+ u32 dsi_con_ctrl;
+ u32 dsi_mode_ctrl;
+ u32 dsi_txrx_ctrl;
+ u32 dsi_psctrl;
+ u32 dsi_vsa_nl;
+ u32 dsi_vbp_nl;
+ u32 dsi_vfp_nl;
+ u32 dsi_vact_nl;
+ u32 dsi_lfr_con; /* Available since MT8183 */
+ u32 dsi_lfr_sta; /* Available since MT8183 */
+ u32 dsi_size_con; /* Available since MT8183 */
+ u32 dsi_vfp_early_stop; /* Available since MT8183 */
+ u32 reserved1[4];
+ u32 dsi_hsa_wc;
+ u32 dsi_hbp_wc;
+ u32 dsi_hfp_wc;
+ u32 dsi_bllp_wc;
+ u32 dsi_cmdq_size;
+ u32 dsi_hstx_cklp_wc;
+ u8 reserved2[156];
+ u32 dsi_phy_lccon;
+ u32 dsi_phy_ld0con;
+ u8 reserved3[4];
+ u32 dsi_phy_timecon0;
+ u32 dsi_phy_timecon1;
+ u32 dsi_phy_timecon2;
+ u32 dsi_phy_timecon3;
+ u8 reserved4[16];
+ u32 dsi_vm_cmd_con;
+ u8 reserved5[92];
+ u32 dsi_force_commit; /* Available since MT8183 */
+ u8 reserved6[108];
+ u32 dsi_cmdq[128];
+};
+
+check_member(dsi_regs, dsi_phy_lccon, 0x104);
+check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
+check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
+check_member(dsi_regs, dsi_force_commit, 0x190);
+check_member(dsi_regs, dsi_cmdq, 0x200);
+
+#endif /* DSI_REGISTER_V1_H */
diff --git a/src/soc/mediatek/common/include/soc/dsi_register_v2.h b/src/soc/mediatek/common/include/soc/dsi_register_v2.h
new file mode 100644
index 0000000000..17809c79ef
--- /dev/null
+++ b/src/soc/mediatek/common/include/soc/dsi_register_v2.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef DSI_REGISTER_V2_H
+#define DSI_REGISTER_V2_H
+
+#include <commonlib/helpers.h>
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct dsi_regs {
+ u32 dsi_start;
+ u8 reserved0[4];
+ u32 dsi_inten;
+ u32 dsi_intsta;
+ u32 dsi_con_ctrl;
+ u32 dsi_mode_ctrl;
+ u32 dsi_txrx_ctrl;
+ u32 dsi_psctrl;
+ u32 dsi_vsa_nl;
+ u32 dsi_vbp_nl;
+ u32 dsi_vfp_nl;
+ u32 dsi_vact_nl;
+ u32 dsi_lfr_con; /* Available since MT8183 */
+ u32 dsi_lfr_sta; /* Available since MT8183 */
+ u32 dsi_size_con; /* Available since MT8183 */
+ u32 dsi_vfp_early_stop; /* Available since MT8183 */
+ u32 reserved1[4];
+ u32 dsi_hsa_wc;
+ u32 dsi_hbp_wc;
+ u32 dsi_hfp_wc;
+ u32 dsi_bllp_wc;
+ u32 dsi_cmdq_size;
+ u32 dsi_hstx_cklp_wc;
+ u8 reserved2[156];
+ u32 dsi_phy_lccon;
+ u32 dsi_phy_ld0con;
+ u8 reserved3[4];
+ u32 dsi_phy_timecon0;
+ u32 dsi_phy_timecon1;
+ u32 dsi_phy_timecon2;
+ u32 dsi_phy_timecon3;
+ u8 reserved4[16];
+ u32 dsi_vm_cmd_con;
+ u8 reserved5[92];
+ u32 dsi_force_commit; /* Available since MT8183 */
+ u8 reserved6[2924];
+ u32 dsi_cmdq[128];
+};
+
+check_member(dsi_regs, dsi_phy_lccon, 0x104);
+check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
+check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
+check_member(dsi_regs, dsi_force_commit, 0x190);
+check_member(dsi_regs, dsi_cmdq, 0xd00);
+
+#endif /* DSI_REGISTER_V2_H */
diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h
index 6f9b301e73..22010c90a1 100644
--- a/src/soc/mediatek/mt8173/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8173/include/soc/dsi.h
@@ -4,6 +4,7 @@
#define _DSI_REG_H_
#include <soc/dsi_common.h>
+#include <soc/dsi_register_v1.h>
#include <types.h>
/* DSI features */
diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h
index 9da79e648c..3fcc281b2d 100644
--- a/src/soc/mediatek/mt8183/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8183/include/soc/dsi.h
@@ -4,6 +4,7 @@
#define SOC_MEDIATEK_MT8183_DSI_H
#include <soc/dsi_common.h>
+#include <soc/dsi_register_v1.h>
#include <types.h>
/* DSI features */
diff --git a/src/soc/mediatek/mt8186/include/soc/dsi.h b/src/soc/mediatek/mt8186/include/soc/dsi.h
index 2cb9159350..1a7c2f992e 100644
--- a/src/soc/mediatek/mt8186/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8186/include/soc/dsi.h
@@ -9,6 +9,7 @@
#define SOC_MEDIATEK_MT8186_DSI_H
#include <soc/dsi_common.h>
+#include <soc/dsi_register_v2.h>
/* DSI features */
#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
diff --git a/src/soc/mediatek/mt8192/include/soc/dsi.h b/src/soc/mediatek/mt8192/include/soc/dsi.h
index ed3d0d8939..9ce55faba6 100644
--- a/src/soc/mediatek/mt8192/include/soc/dsi.h
+++ b/src/soc/mediatek/mt8192/include/soc/dsi.h
@@ -4,6 +4,7 @@
#define SOC_MEDIATEK_MT8192_DSI_H
#include <soc/dsi_common.h>
+#include <soc/dsi_register_v1.h>
/* DSI features */
#define MTK_DSI_MIPI_RATIO_NUMERATOR 100
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 10:01:04 +0000