diff options
Diffstat (limited to 'src/soc/mediatek/mt8192/include')
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/addressmap.h | 2 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/clkbuf.h | 69 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/pmif.h | 31 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/rtc.h | 14 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8192/include/soc/srclken_rc.h | 191 |
5 files changed, 293 insertions, 14 deletions
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h index e4d57b05fc..3a07802f8d 100644 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -20,6 +20,8 @@ enum { INFRACFG_AO_MEM_BASE = IO_PHYS + 0x00002000, GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, + RC_BASE = IO_PHYS + 0x00006500, + RC_STATUS_BASE = IO_PHYS + 0x00006E00, RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, EINT_BASE = IO_PHYS + 0x0000B000, diff --git a/src/soc/mediatek/mt8192/include/soc/clkbuf.h b/src/soc/mediatek/mt8192/include/soc/clkbuf.h new file mode 100644 index 0000000000..b5fa3a3f1b --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/clkbuf.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_CLKBUF_H +#define SOC_MEDIATEK_MT8192_CLKBUF_H + +#include <device/mmio.h> + +enum { + PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW02 = 0x0790, + PMIC_RG_DCXO_CW08 = 0x079C, + PMIC_RG_DCXO_CW09 = 0x079E, + PMIC_RG_DCXO_CW09_CLR = 0x07A2, + PMIC_RG_DCXO_CW10 = 0x07A4, + PMIC_RG_DCXO_CW12 = 0x07A8, + PMIC_RG_DCXO_CW13 = 0x07AA, + PMIC_RG_DCXO_CW15 = 0x07AE, + PMIC_RG_DCXO_CW19 = 0x07B6, +}; + +enum { + PMIC_TOP_TMA_KEY = 0x3A8, + PMIC_RG_TOP_SPI_CON1 = 0x458, +}; + +enum { + PMIC_TOP_TMA_KEY_UNLOCK = 0x9CA6, +}; + +enum { + PMIC_RG_LDO_VRFCK_ELR = 0x1B40, + PMIC_RG_LDO_VRFCK_CON0 = 0x1D1C, + PMIC_RG_LDO_VRFCK_OP_EN = 0x1D22, + PMIC_RG_LDO_VRFCK_OP_EN_SET = 0x1D24, + PMIC_RG_LDO_VBBCK_CON0 = 0x1D2E, + PMIC_RG_LDO_VBBCK_OP_EN = 0x1D34, + PMIC_RG_LDO_VBBCK_OP_EN_SET = 0x1D36, +}; + +enum { + PMIC_RG_DCXO_ADLDO_BIAS_ELR_0 = 0x209C, + PMIC_RG_DCXO_ADLDO_BIAS_ELR_1 = 0x209E, +}; + +enum { + PMIC_RG_XO_BUF_CTL0 = 0x54C, + PMIC_RG_XO_BUF_CTL1 = 0x54E, + PMIC_RG_XO_BUF_CTL2 = 0x550, + PMIC_RG_XO_BUF_CTL3 = 0x552, + PMIC_RG_XO_BUF_CTL4 = 0x554, + PMIC_RG_XO_CONN_BT0 = 0x556, +}; + +DEFINE_BITFIELD(PMIC_REG_COMMON, 15, 0) +DEFINE_BIT(PMIC_RG_VRFCK_HV_EN, 9) +DEFINE_BIT(PMIC_RG_LDO_VRFCK_EN, 0) +DEFINE_BIT(PMIC_RG_LDO_VRFCK_ANA_SEL, 0) +DEFINE_BIT(PMIC_RG_LDO_VBBCK_EN, 0) +DEFINE_BIT(PMIC_RG_VRFCK_NDIS_EN, 11) +DEFINE_BIT(PMIC_RG_VRFCK_1_NDIS_EN, 0) +DEFINE_BIT(PMIC_RG_LDO_VRFCK_HW14_OP_EN, 14) +DEFINE_BIT(PMIC_RG_LDO_VBBCK_HW14_OP_EN, 14) +DEFINE_BIT(PMIC_RG_SRCLKEN_IN3_EN, 0) +DEFINE_BIT(PMIC_RG_XO_PMIC_TOP_DIG_SW, 2) +DEFINE_BITFIELD(PMIC_RG_XO_VOTE, 10, 0) + +int clk_buf_init(void); + +#endif /* SOC_MEDIATEK_MT8192_CLKBUF_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/pmif.h b/src/soc/mediatek/mt8192/include/soc/pmif.h index fe3def020a..cfc7fe5f1e 100644 --- a/src/soc/mediatek/mt8192/include/soc/pmif.h +++ b/src/soc/mediatek/mt8192/include/soc/pmif.h @@ -3,6 +3,7 @@ #ifndef __MT8192_SOC_PMIF_H__ #define __MT8192_SOC_PMIF_H__ +#include <device/mmio.h> #include <types.h> enum { @@ -167,6 +168,36 @@ enum { E_SPI_INIT_SIDLY, /* SPI edge calibration fail */ }; +enum pmic_interface { + PMIF_VLD_RDY = 0, + PMIF_SLP_REQ, +}; + +DEFINE_BIT(PMIFSPI_INF_EN_SRCLKEN_RC_HW, 4) + +DEFINE_BIT(PMIFSPI_OTHER_INF_DXCO0_EN, 0) +DEFINE_BIT(PMIFSPI_OTHER_INF_DXCO1_EN, 1) + +DEFINE_BIT(PMIFSPI_ARB_EN_SRCLKEN_RC_HW, 4) +DEFINE_BIT(PMIFSPI_ARB_EN_DCXO_CONN, 15) +DEFINE_BIT(PMIFSPI_ARB_EN_DCXO_NFC, 16) + +DEFINE_BITFIELD(PMIFSPI_SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(PMIFSPI_SCP_SLEEP_REQ_SEL, 10, 9) + +DEFINE_BIT(PMIFSPI_MD_CTL_PMIF_RDY, 9) +DEFINE_BIT(PMIFSPI_MD_CTL_SRCLK_EN, 10) +DEFINE_BIT(PMIFSPI_MD_CTL_SRVOL_EN, 11) + +DEFINE_BITFIELD(PMIFSPMI_SPM_SLEEP_REQ_SEL, 1, 0) +DEFINE_BITFIELD(PMIFSPMI_SCP_SLEEP_REQ_SEL, 10, 9) + +DEFINE_BIT(PMIFSPMI_MD_CTL_PMIF_RDY, 9) +DEFINE_BIT(PMIFSPMI_MD_CTL_SRCLK_EN, 10) +DEFINE_BIT(PMIFSPMI_MD_CTL_SRVOL_EN, 11) + +/* External API */ extern struct pmif *get_pmif_controller(int inf, int mstid); +extern void pmwrap_interface_init(void); extern int mtk_pmif_init(void); #endif /*__MT8192_SOC_PMIF_H__*/ diff --git a/src/soc/mediatek/mt8192/include/soc/rtc.h b/src/soc/mediatek/mt8192/include/soc/rtc.h index 491aeabc37..46c06f4a52 100644 --- a/src/soc/mediatek/mt8192/include/soc/rtc.h +++ b/src/soc/mediatek/mt8192/include/soc/rtc.h @@ -149,19 +149,6 @@ enum { PMIC_RG_BANK_FQMTR_RST_SHIFT = 6, }; -/* PMIC DCXO Register Definition */ -enum { - PMIC_RG_DCXO_CW00 = 0x0788, - PMIC_RG_DCXO_CW00_SET = 0x078A, - PMIC_RG_DCXO_CW00_CLR = 0x078C, - PMIC_RG_DCXO_CW02 = 0x0790, - PMIC_RG_DCXO_CW08 = 0x079C, - PMIC_RG_DCXO_CW09 = 0x079E, - PMIC_RG_DCXO_CW09_SET = 0x07A0, - PMIC_RG_DCXO_CW09_CLR = 0x07A2, - PMIC_RG_DCXO_CW12 = 0x07A8, -}; - /* PMIC Frequency Meter Definition */ enum { PMIC_RG_FQMTR_CKSEL = 0x0118, @@ -228,5 +215,4 @@ int rtc_init(int recover); bool rtc_gpio_init(void); void rtc_boot(void); u16 rtc_get_frequency_meter(u16 val, u16 measure_src, u16 window_size); -void mt6359_dcxo_disable_unused(void); #endif /* SOC_MEDIATEK_MT8192_RTC_H */ diff --git a/src/soc/mediatek/mt8192/include/soc/srclken_rc.h b/src/soc/mediatek/mt8192/include/soc/srclken_rc.h new file mode 100644 index 0000000000..dc0a076087 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/srclken_rc.h @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_SRCLKEN_RC_H +#define SOC_MEDIATEK_MT8192_SRCLKEN_RC_H + +#include <device/mmio.h> + +struct mtk_rc_regs { + u32 srclken_rc_cfg; + u32 rc_central_cfg1; + u32 rc_central_cfg2; + u32 rc_cmd_arb_cfg; + u32 rc_pmic_rcen_addr; + u32 rc_pmic_rcen_set_clr_addr; + u32 rc_dcxo_fpm_cfg; + u32 rc_central_cfg3; + u32 rc_mxx_srclken_cfg[13]; + u32 srclken_sw_con_cfg; + u32 rc_central_cfg4; + u32 reserved1; + u32 rc_protocol_chk_cfg; + u32 rc_debug_cfg; + u32 reserved2[19]; + u32 rc_misc_0; + u32 rc_spm_ctrl; + u32 rc_subsys_intf_cfg; +}; + +check_member(mtk_rc_regs, rc_central_cfg1, 0x4); +check_member(mtk_rc_regs, rc_mxx_srclken_cfg[0], 0x20); +check_member(mtk_rc_regs, rc_mxx_srclken_cfg[12], 0x50); +check_member(mtk_rc_regs, rc_central_cfg4, 0x58); +check_member(mtk_rc_regs, rc_protocol_chk_cfg, 0x60); +check_member(mtk_rc_regs, rc_misc_0, 0xb4); +check_member(mtk_rc_regs, rc_subsys_intf_cfg, 0xbc); + +struct mtk_rc_status_regs { + u32 rc_fsm_sta_0; + u32 rc_cmd_sta_0; + u32 rc_cmd_sta_1; + u32 rc_spi_sta_0; + u32 rc_pi_po_sta_0; + u32 rc_mxx_req_sta_0[14]; + u32 reserved2[2]; + u32 rc_debug_trace; +}; + +check_member(mtk_rc_status_regs, rc_cmd_sta_1, 0x8); +check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[0], 0x14); +check_member(mtk_rc_status_regs, rc_mxx_req_sta_0[13], 0x48); +check_member(mtk_rc_status_regs, rc_debug_trace, 0x54); + +/* SPM Register */ +/* SRCLKEN_RC_CFG */ +DEFINE_BIT(SW_RESET, 0) +DEFINE_BIT(CG_32K_EN, 1) +DEFINE_BIT(CG_FCLK_EN, 2) +DEFINE_BIT(CG_FCLK_FR_EN, 3) +DEFINE_BIT(MUX_FCLK_FR, 4) + +/* RC_CENTRAL_CFG1 */ +DEFINE_BIT(SRCLKEN_RC_EN, 0) +DEFINE_BIT(RCEN_ISSUE_M, 1) +DEFINE_BIT(RC_SPI_ACTIVE, 2) +DEFINE_BIT(SRCLKEN_RC_EN_SEL, 3) +DEFINE_BITFIELD(VCORE_SETTLE_T, 7, 5) +DEFINE_BITFIELD(ULPOSC_SETTLE_T, 11, 8) +DEFINE_BITFIELD(NON_DCXO_SETTLE_T, 21, 12) +DEFINE_BITFIELD(DCXO_SETTLE_T, 31, 22) + +/* RC_CENTRAL_CFG2 */ +DEFINE_BITFIELD(SRCVOLTEN_CTRL, 3, 0) +DEFINE_BITFIELD(VREQ_CTRL, 7, 4) +DEFINE_BIT(SRCVOLTEN_VREQ_SEL, 8) +DEFINE_BIT(SRCVOLTEN_VREQ_M, 9) +DEFINE_BITFIELD(ULPOSC_CTRL_M, 15, 12) +DEFINE_BITFIELD(PWRAP_SLP_CTRL_M, 24, 21) +DEFINE_BIT(PWRAP_SLP_MUX_SEL, 25) + +/* RC_DCXO_FPM_CFG */ +DEFINE_BITFIELD(DCXO_FPM_CTRL_M, 3, 0) +DEFINE_BIT(SRCVOLTEN_FPM_MSK_B, 4) +DEFINE_BITFIELD(SUB_SRCLKEN_FPM_MSK_B, 28, 16) + +/* RC_CENTRAL_CFG3 */ +DEFINE_BIT(TO_LPM_SETTLE_EN, 0) +DEFINE_BIT(BLK_SCP_DXCO_MD_TARGET, 1) +DEFINE_BIT(BLK_COANT_DXCO_MD_TARGET, 2) +DEFINE_BIT(TO_BBLPM_SETTLE_EN, 3) +DEFINE_BITFIELD(TO_LPM_SETTLE_T, 21, 12) + +/* RC_CENTRAL_CFG4 */ +DEFINE_BITFIELD(KEEP_RC_SPI_ACTIVE, 8, 0) +DEFINE_BIT(PWRAP_VLD_FORCE, 16) +DEFINE_BIT(SLEEP_VLD_MODE, 17) + +/* RC_MXX_SRCLKEN_CFG */ +DEFINE_BIT(DCXO_SETTLE_BLK_EN, 1) +DEFINE_BIT(BYPASS_CMD_EN, 2) +DEFINE_BIT(SW_SRCLKEN_RC, 3) +DEFINE_BIT(SW_SRCLKEN_FPM, 4) +DEFINE_BIT(SW_SRCLKEN_BBLPM, 5) +DEFINE_BIT(XO_SOC_LINK_EN, 6) +DEFINE_BIT(REQ_ACK_LOW_IMD_EN, 7) +DEFINE_BIT(SRCLKEN_TRACK_M_EN, 8) +DEFINE_BITFIELD(CNT_PRD_STEP, 11, 10) +DEFINE_BITFIELD(XO_STABLE_PRD, 21, 12) +DEFINE_BITFIELD(DCXO_STABLE_PRD, 31, 22) + +enum { + SW_SRCLKEN_FPM_MSK = 0x1, + SW_SRCLKEN_BBLPM_MSK = 0x1, +}; + +/* RC_DEBUG_CFG */ +DEFINE_BIT(TRACE_MODE_EN, 24) + +/* SUBSYS_INTF_CFG */ +DEFINE_BITFIELD(SRCLKEN_FPM_MASK_B, 12, 0) +DEFINE_BITFIELD(SRCLKEN_BBLPM_MASK_B, 28, 16) + +enum { + PMIC_PMRC_CON0 = 0x1A6, + PMIC_PMRC_CON0_SET = 0x1A8, + PMIC_PMRC_CON0_CLR = 0x1AA, +}; + +enum chn_id { + CHN_SUSPEND = 0, + CHN_RF = 1, + CHN_DEEPIDLE = 2, + CHN_MD = 3, + CHN_GPS = 4, + CHN_BT = 5, + CHN_WIFI = 6, + CHN_MCU = 7, + CHN_COANT = 8, + CHN_NFC = 9, + CHN_UFS = 10, + CHN_SCP = 11, + CHN_RESERVE = 12, + MAX_CHN_NUM, +}; + +enum { + SRCLKENAO_MODE, + VREQ_MODE, +}; + +enum { + MERGE_OR_MODE = 0x0, + BYPASS_MODE = 0x1, + MERGE_AND_MODE = 0x1 << 1, + BYPASS_RC_MODE = 0x2 << 1, + BYPASS_OTHER_MODE = 0x3 << 1, + ASYNC_MODE = 0x1 << 3, +}; + +enum { + RC_32K = 0, + RC_ULPOSC1, +}; + +enum rc_ctrl_m { + HW_MODE = 0, + SW_MODE = 1, + INIT_MODE = 0xff, +}; + +enum rc_support { + SRCLKEN_RC_ENABLE = 0, + SRCLKEN_RC_DISABLE, +}; + +struct subsys_rc_con { + unsigned int dcxo_prd; + unsigned int xo_prd; + unsigned int cnt_step; + unsigned int track_en; + unsigned int req_ack_imd_en; + unsigned int xo_soc_link_en; + unsigned int sw_bblpm; + unsigned int sw_fpm; + unsigned int sw_rc; + unsigned int bypass_cmd; + unsigned int dcxo_settle_blk_en; +}; + +extern int srclken_rc_init(void); + +#endif /* SOC_MEDIATEK_MT8192_SRCLKEN_RC_H */ |