diff options
Diffstat (limited to 'src/soc/mediatek/mt8192/dramc_pi_main.c')
-rw-r--r-- | src/soc/mediatek/mt8192/dramc_pi_main.c | 182 |
1 files changed, 182 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index 8eba016dd8..0373c8212c 100644 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -6,6 +6,186 @@ #include <soc/pll_common.h> #include <soc/regulator.h> +static void dramc_ac_timing_optimize(const struct ddr_cali *cali) +{ + u8 rf_group, cab_id; + u8 trfc, trfc_05t, trfc_pb, trfrc_pb05t, tx_ref_cnt; + + enum { + TRFCAB_130, + TRFCAB_180, + TRFCAB_280, + TRFCAB_380, + TRFCAB_NUM, + }; + enum { + GRP_DDR800_DIV4_ACTIM, + GRP_DDR1200_ACTIM, + GRP_DDR1600_ACTIM, + GRP_DDR1866_ACTIM, + GRP_DDR2400_ACTIM, + GRP_DDR3200_ACTIM, + GRP_DDR4266_ACTIM, + GRP_ACTIM_NUM, + }; + struct optimize_ac_time { + u8 trfc; + u8 trfc_05t; + u8 trfc_pb; + u8 trfrc_pb05t; + u16 tx_ref_cnt; + }; + + const u8 density = cali->density; + const dram_freq_grp freq_group = get_freq_group(cali); + + /* tRFCab */ + struct optimize_ac_time *ptr_trfcab_opt; + struct optimize_ac_time trfcab_opt[GRP_ACTIM_NUM][TRFCAB_NUM] = { + [GRP_DDR800_DIV4_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, + .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1200_ACTIM] = { + {.trfc = 8, .trfc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 21}, + {.trfc = 15, .trfc_05t = 1, .trfc_pb = 2, + .trfrc_pb05t = 0, .tx_ref_cnt = 29}, + {.trfc = 30, .trfc_05t = 1, .trfc_pb = 9, + .trfrc_pb05t = 1, .tx_ref_cnt = 44}, + {.trfc = 45, .trfc_05t = 1, .trfc_pb = 17, + .trfrc_pb05t = 0, .tx_ref_cnt = 59} + }, + [GRP_DDR1600_ACTIM] = { + {.trfc = 14, .trfc_05t = 0, .trfc_pb = 0, + .trfrc_pb05t = 0, .tx_ref_cnt = 28}, + {.trfc = 24, .trfc_05t = 0, .trfc_pb = 6, + .trfrc_pb05t = 0, .tx_ref_cnt = 38}, + {.trfc = 44, .trfc_05t = 0, .trfc_pb = 16, + .trfrc_pb05t = 0, .tx_ref_cnt = 58}, + {.trfc = 64, .trfc_05t = 0, .trfc_pb = 26, + .trfrc_pb05t = 0, .tx_ref_cnt = 78} + }, + [GRP_DDR1866_ACTIM] = { + {.trfc = 18, .trfc_05t = 1, .trfc_pb = 2, + .trfrc_pb05t = 0, .tx_ref_cnt = 33}, + {.trfc = 30, .trfc_05t = 0, .trfc_pb = 9, + .trfrc_pb05t = 0, .tx_ref_cnt = 44}, + {.trfc = 53, .trfc_05t = 1, .trfc_pb = 21, + .trfrc_pb05t = 0, .tx_ref_cnt = 68}, + {.trfc = 77, .trfc_05t = 0, .trfc_pb = 32, + .trfrc_pb05t = 1, .tx_ref_cnt = 91} + }, + [GRP_DDR2400_ACTIM] = { + {.trfc = 27, .trfc_05t = 1, .trfc_pb = 6, + .trfrc_pb05t = 1, .tx_ref_cnt = 42}, + {.trfc = 42, .trfc_05t = 1, .trfc_pb = 15, + .trfrc_pb05t = 1, .tx_ref_cnt = 57}, + {.trfc = 72, .trfc_05t = 1, .trfc_pb = 30, + .trfrc_pb05t = 1, .tx_ref_cnt = 87}, + {.trfc = 102, .trfc_05t = 1, .trfc_pb = 45, + .trfrc_pb05t = 1, .tx_ref_cnt = 117} + }, + [GRP_DDR3200_ACTIM] = { + {.trfc = 40, .trfc_05t = 0, .trfc_pb = 12, + .trfrc_pb05t = 0, .tx_ref_cnt = 55}, + {.trfc = 60, .trfc_05t = 0, .trfc_pb = 24, + .trfrc_pb05t = 0, .tx_ref_cnt = 75}, + {.trfc = 100, .trfc_05t = 0, .trfc_pb = 44, + .trfrc_pb05t = 0, .tx_ref_cnt = 115}, + {.trfc = 140, .trfc_05t = 0, .trfc_pb = 64, + .trfrc_pb05t = 0, .tx_ref_cnt = 155} + }, + [GRP_DDR4266_ACTIM] = { + {.trfc = 57, .trfc_05t = 1, .trfc_pb = 20, + .trfrc_pb05t = 0, .tx_ref_cnt = 74}, + {.trfc = 84, .trfc_05t = 0, .trfc_pb = 36, + .trfrc_pb05t = 0, .tx_ref_cnt = 100}, + {.trfc = 137, .trfc_05t = 1, .trfc_pb = 63, + .trfrc_pb05t = 0, .tx_ref_cnt = 154}, + {.trfc = 191, .trfc_05t = 0, .trfc_pb = 89, + .trfrc_pb05t = 1, .tx_ref_cnt = 207} + } + }; + + switch (density) { + case 0x0: + rf_group = TRFCAB_130; + break; + case 0x1: + case 0x2: + rf_group = TRFCAB_180; + break; + case 0x3: + case 0x4: + rf_group = TRFCAB_280; + break; + case 0x5: + case 0x6: + rf_group = TRFCAB_380; + break; + default: + die("Invalid DDR density %u\n", density); + return; + } + + switch (freq_group) { + case DDRFREQ_400: + cab_id = GRP_DDR800_DIV4_ACTIM; + break; + case DDRFREQ_600: + cab_id = GRP_DDR1200_ACTIM; + break; + case DDRFREQ_800: + cab_id = GRP_DDR1600_ACTIM; + break; + case DDRFREQ_933: + cab_id = GRP_DDR1866_ACTIM; + break; + case DDRFREQ_1200: + cab_id = GRP_DDR2400_ACTIM; + break; + case DDRFREQ_1600: + cab_id = GRP_DDR3200_ACTIM; + break; + case DDRFREQ_2133: + cab_id = GRP_DDR4266_ACTIM; + break; + default: + die("Invalid DDR frequency group %u\n", freq_group); + return; + } + + ptr_trfcab_opt = &trfcab_opt[cab_id][0]; + trfc = ptr_trfcab_opt[rf_group].trfc; + trfc_05t = ptr_trfcab_opt[rf_group].trfc_05t; + trfc_pb = ptr_trfcab_opt[rf_group].trfc_pb; + trfrc_pb05t = ptr_trfcab_opt[rf_group].trfrc_pb05t; + tx_ref_cnt = ptr_trfcab_opt[rf_group].tx_ref_cnt; + + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFC, trfc); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFC_05T, trfc_05t); + SET32_BITFIELDS(&ch[chn].ao.shu_actim4, + SHU_ACTIM4_TXREFCNT, tx_ref_cnt); + SET32_BITFIELDS(&ch[chn].ao.shu_actim3, + SHU_ACTIM3_TRFCPB, trfc_pb); + SET32_BITFIELDS(&ch[chn].ao.shu_ac_time_05t, + SHU_AC_TIME_05T_TRFCPB_05T, trfrc_pb05t); + dramc_dbg("Density (MR8 OP[5:2]) %u, TRFC %u, TRFC_05T %u, TXREFCNT %u, " + "TRFCpb %u, TRFCpb_05T %u\n", + density, trfc, trfc_05t, tx_ref_cnt, trfc_pb, trfrc_pb05t); + } +} + static void set_vcore_voltage(const struct ddr_cali *cali) { u32 vcore = get_vcore_value(cali); @@ -140,6 +320,8 @@ void init_dram(const struct dramc_data *dparam) if (first_freq_k) get_dram_info_after_cal(&cali); + dramc_ac_timing_optimize(&cali); + first_freq_k = false; } } |