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-rw-r--r--src/soc/mediatek/mt8183/include/soc/ddp.h1
-rw-r--r--src/soc/mediatek/mt8183/pmic_wrap.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/mediatek/mt8183/include/soc/ddp.h b/src/soc/mediatek/mt8183/include/soc/ddp.h
index bc4e6ab501..a059abf566 100644
--- a/src/soc/mediatek/mt8183/include/soc/ddp.h
+++ b/src/soc/mediatek/mt8183/include/soc/ddp.h
@@ -42,7 +42,6 @@ check_member(mmsys_cfg_regs, dpi0_sel_sout_sel_in, 0xF64);
static struct mmsys_cfg_regs *const mmsys_cfg =
(void *)MMSYS_BASE;
-
/* DISP_REG_CONFIG_MMSYS_CG_CON0
Configures free-run clock gating 0
0: Enable clock
diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c
index bae3fce5bf..4d195b79f0 100644
--- a/src/soc/mediatek/mt8183/pmic_wrap.c
+++ b/src/soc/mediatek/mt8183/pmic_wrap.c
@@ -47,7 +47,6 @@ enum {
COUNTER16_PENDING_THRES = STARVE_ENABLE | PENDING_US(0x340),
};
-
static void pwrap_soft_reset(void)
{
write32(&mt8183_infracfg->infra_globalcon_rst2_set, 0x1);