diff options
Diffstat (limited to 'src/soc/mediatek/mt8173')
| -rw-r--r-- | src/soc/mediatek/mt8173/Makefile.inc | 8 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/gpio.c | 153 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/gpio_init.c | 12 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/gpio.h | 314 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/include/soc/pinmux.h | 166 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8173/spi.c | 9 |
6 files changed, 327 insertions, 335 deletions
diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 003feabece..1a5ee80c07 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -27,7 +27,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c endif -bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c +bootblock-y += ../common/gpio.c gpio.c gpio_init.c pmic_wrap.c mt6391.c bootblock-y += ../common/wdt.c bootblock-y += ../common/mmu_operations.c mmu_operations.c @@ -42,7 +42,7 @@ verstage-y += ../common/timer.c verstage-y += timer.c verstage-y += ../common/wdt.c verstage-$(CONFIG_SPI_FLASH) += flash_controller.c -verstage-y += gpio.c +verstage-y += ../common/gpio.c gpio.c ################################################################################ @@ -54,7 +54,7 @@ romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c romstage-y += ../common/cbmem.c romstage-y += spi.c -romstage-y += gpio.c +romstage-y += ../common/gpio.c gpio.c romstage-y += pmic_wrap.c mt6391.c romstage-y += memory.c romstage-y += emi.c dramc_pi_basic_api.c dramc_pi_calibration_api.c @@ -73,7 +73,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c ramstage-y += pmic_wrap.c mt6391.c i2c.c ramstage-y += mt6311.c ramstage-y += da9212.c -ramstage-y += gpio.c +ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/wdt.c ramstage-y += ../common/pll.c pll.c ramstage-y += rtc.c diff --git a/src/soc/mediatek/mt8173/gpio.c b/src/soc/mediatek/mt8173/gpio.c index c5ca08b923..518df851f1 100644 --- a/src/soc/mediatek/mt8173/gpio.c +++ b/src/soc/mediatek/mt8173/gpio.c @@ -14,80 +14,38 @@ */ #include <arch/io.h> #include <assert.h> -#include <console/console.h> #include <gpio.h> #include <types.h> -#include <soc/addressmap.h> -#include <soc/gpio.h> enum { - MAX_8173_GPIO = 134, - MAX_GPIO_REG_BITS = 16, - MAX_GPIO_MODE_PER_REG = 5, - GPIO_MODE_BITS = 3, + MAX_GPIO_NUMBER = 134, MAX_EINT_REG_BITS = 32, }; -enum { - GPIO_DIRECTION_IN = 0, - GPIO_DIRECTION_OUT = 1, -}; - -enum { - GPIO_MODE = 0, -}; - -static void pos_bit_calc(u32 pin, u32 *pos, u32 *bit) +static void pos_bit_calc(gpio_t gpio, u32 *pos, u32 *bit) { - *pos = pin / MAX_GPIO_REG_BITS; - *bit = pin % MAX_GPIO_REG_BITS; + *pos = gpio.id / MAX_GPIO_REG_BITS; + *bit = gpio.id % MAX_GPIO_REG_BITS; } -static void pos_bit_calc_for_mode(u32 pin, u32 *pos, u32 *bit) +static void pos_bit_calc_for_eint(gpio_t gpio, u32 *pos, u32 *bit) { - *pos = pin / MAX_GPIO_MODE_PER_REG; - *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; -} - -static void pos_bit_calc_for_eint(u32 pin, u32 *pos, u32 *bit) -{ - *pos = pin / MAX_EINT_REG_BITS; - *bit = pin % MAX_EINT_REG_BITS; -} - -static s32 gpio_set_dir(u32 pin, u32 dir) -{ - u32 pos; - u32 bit; - u16 *reg; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - if (dir == GPIO_DIRECTION_IN) - reg = &mt8173_gpio->dir[pos].rst; - else - reg = &mt8173_gpio->dir[pos].set; - - write16(reg, 1L << bit); - - return 0; + *pos = gpio.id / MAX_EINT_REG_BITS; + *bit = gpio.id % MAX_EINT_REG_BITS; } -void gpio_set_pull(gpio_t pin, enum pull_enable enable, +void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select) { u32 pos; u32 bit; - u16 *en_reg, *sel_reg; + u32 *en_reg, *sel_reg; + u32 pin = gpio.id; - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); + pos_bit_calc(gpio, &pos, &bit); if (enable == GPIO_PULL_DISABLE) { - en_reg = &mt8173_gpio->pullen[pos].rst; + en_reg = &mtk_gpio->pullen[pos].rst; } else { /* These pins' pulls can't be set through GPIO controller. */ assert(pin < 22 || pin > 27); @@ -97,100 +55,21 @@ void gpio_set_pull(gpio_t pin, enum pull_enable enable, assert(pin < 100 || pin > 105); assert(pin < 119 || pin > 124); - en_reg = &mt8173_gpio->pullen[pos].set; + en_reg = &mtk_gpio->pullen[pos].set; sel_reg = (select == GPIO_PULL_DOWN) ? - (&mt8173_gpio->pullsel[pos].rst) : - (&mt8173_gpio->pullsel[pos].set); + (&mtk_gpio->pullsel[pos].rst) : + (&mtk_gpio->pullsel[pos].set); write16(sel_reg, 1L << bit); } write16(en_reg, 1L << bit); } -int gpio_get(gpio_t pin) -{ - u32 pos; - u32 bit; - u16 *reg; - s32 data; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - reg = &mt8173_gpio->din[pos].val; - data = read32(reg); - - return (data & (1L << bit)) ? 1 : 0; -} - -void gpio_set(gpio_t pin, int output) -{ - u32 pos; - u32 bit; - u16 *reg; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc(pin, &pos, &bit); - - if (output == 0) - reg = &mt8173_gpio->dout[pos].rst; - else - reg = &mt8173_gpio->dout[pos].set; - write16(reg, 1L << bit); -} - -void gpio_set_mode(gpio_t pin, int mode) -{ - u32 pos; - u32 bit; - u32 mask = (1L << GPIO_MODE_BITS) - 1; - - assert(pin <= MAX_8173_GPIO); - - pos_bit_calc_for_mode(pin, &pos, &bit); - - clrsetbits_le32(&mt8173_gpio->mode[pos].val, - mask << bit, mode << bit); -} - -void gpio_input_pulldown(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_DOWN); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_input_pullup(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_ENABLE, GPIO_PULL_UP); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_input(gpio_t gpio) -{ - gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); - gpio_set_dir(gpio, GPIO_DIRECTION_IN); - gpio_set_mode(gpio, GPIO_MODE); -} - -void gpio_output(gpio_t gpio, int value) -{ - gpio_set_pull(gpio, GPIO_PULL_DISABLE, GPIO_PULL_DOWN); - gpio_set(gpio, value); - gpio_set_dir(gpio, GPIO_DIRECTION_OUT); - gpio_set_mode(gpio, GPIO_MODE); -} - int gpio_eint_poll(gpio_t gpio) { u32 pos; u32 bit; u32 status; - assert(gpio <= MAX_8173_GPIO); - pos_bit_calc_for_eint(gpio, &pos, &bit); status = (read32(&mt8173_eint->sta.regs[pos]) >> bit) & 0x1; @@ -206,8 +85,6 @@ void gpio_eint_configure(gpio_t gpio, enum gpio_irq_type type) u32 pos; u32 bit, mask; - assert(gpio <= MAX_8173_GPIO); - pos_bit_calc_for_eint(gpio, &pos, &bit); mask = 1 << bit; diff --git a/src/soc/mediatek/mt8173/gpio_init.c b/src/soc/mediatek/mt8173/gpio_init.c index 7f8313aafb..79ed316cb5 100644 --- a/src/soc/mediatek/mt8173/gpio_init.c +++ b/src/soc/mediatek/mt8173/gpio_init.c @@ -49,18 +49,18 @@ static void gpio_set_duty(enum external_power ext_power) /* EXMD control reg */ if (ext_power == GPIO_EINT_1P8V) { /* exmd_ctrl[9:4] = b`000000, [3:0] = b`1010 */ - write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x3F5); - write16(&mt8173_gpio->exmd_ctrl[0].set, 0xA); + write16(&mtk_gpio->exmd_ctrl[0].rst, 0x3F5); + write16(&mtk_gpio->exmd_ctrl[0].set, 0xA); } else if (ext_power == GPIO_EINT_3P3V) { /* exmd_ctrl[9:4] = b`001100, [3:0] = b`1010 */ - write16(&mt8173_gpio->exmd_ctrl[0].rst, 0x335); - write16(&mt8173_gpio->exmd_ctrl[0].set, 0xCA); + write16(&mtk_gpio->exmd_ctrl[0].rst, 0x335); + write16(&mtk_gpio->exmd_ctrl[0].set, 0xCA); } /* other R/TDSEL */ /* msdc2_ctrl5 , bit[3:0] = b`1010 */ - write16(&mt8173_gpio->msdc2_ctrl5.set, 0xA); - write16(&mt8173_gpio->msdc2_ctrl5.rst, 0x5); + write16(&mtk_gpio->msdc2_ctrl5.set, 0xA); + write16(&mtk_gpio->msdc2_ctrl5.rst, 0x5); } void gpio_init(enum external_power ext_power) diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index 1c05e48b14..a78c8b4fa0 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -18,15 +18,12 @@ #include <stdint.h> #include <stdlib.h> #include <soc/addressmap.h> +#include <soc/gpio_common.h> -enum pull_enable { - GPIO_PULL_DISABLE = 0, - GPIO_PULL_ENABLE = 1, -}; - -enum pull_select { - GPIO_PULL_DOWN = 0, - GPIO_PULL_UP = 1, +enum { + MAX_GPIO_REG_BITS = 16, + MAX_GPIO_MODE_PER_REG = 5, + GPIO_MODE_BITS = 3, }; enum external_power { @@ -34,15 +31,300 @@ enum external_power { GPIO_EINT_1P8V = 1, }; -typedef u32 gpio_t; +typedef struct { + u32 id; +} gpio_t; + +#define PIN(id, name, func1, func2, func3, func4, func5, func6, func7) \ + PAD_##name##_ID = id, \ + PAD_##name##_FUNC_##func1 = 1, \ + PAD_##name##_FUNC_##func2 = 2, \ + PAD_##name##_FUNC_##func3 = 3, \ + PAD_##name##_FUNC_##func4 = 4, \ + PAD_##name##_FUNC_##func5 = 5, \ + PAD_##name##_FUNC_##func6 = 6, \ + PAD_##name##_FUNC_##func7 = 7 + +#define GPIO(name) ((gpio_t){.id = PAD_##name##_ID}) + +enum { + PIN(0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, + UTXD0, RES5, RES6, DBG_MON_A_20), + PIN(1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, + URXD0, RES5, RES6, DBG_MON_A_21), + PIN(2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, + UTXD3, RES5, RES6, DBG_MON_A_22), + PIN(3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, + URXD3, RES5, RES6, DBG_MON_A_23), + PIN(4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, + UCTS3, RES5, SFWP_B, RES7), + PIN(5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, + URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7), + PIN(6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, + RES4, AP_MD32_JTAG_TCK, SFCS0, RES7), + PIN(7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, + RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7), + PIN(8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, + AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7), + PIN(9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, + USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7), + PIN(10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, + PWM4, IRDA_RXD, RES6, RES7), + PIN(11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, + PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30), + PIN(12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, + RES4, I2S2_WS, RES6, DBG_MON_B_32), + PIN(13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, + RES4, I2S2_BCK, RES6, DBG_MON_A_32), + PIN(14, EINT14, CMDAT0, CMCSD0, RES3, + CLKM2, RES5, RES6, DBG_MON_B_6), + PIN(15, EINT15, CMDAT1, CMCSD1, CMFLASH, + CLKM3, RES5, RES6, DBG_MON_B_29), + PIN(16, IDDIG, IDDIG, CMFLASH, RES3, + PWM5, RES5, RES6, RES7), + PIN(17, WATCHDOG, WATCHDOG_AO, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(18, CEC, CEC, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(19, HDMISCK, HDMISCK, HDCP_SCL, RES3, + RES4, RES5, RES6, RES7), + PIN(20, HDMISD, HDMISD, HDCP_SDA, RES3, + RES4, RES5, RES6, RES7), + PIN(21, HTPLG, HTPLG, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(29, UCTS2, UCTS2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(30, URTS2, URTS2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(31, URXD2, URXD2, UTXD2, RES3, + RES4, RES5, RES6, RES7), + PIN(32, UTXD2, UTXD2, URXD2, RES3, + RES4, RES5, RES6, RES7), + PIN(33, DAICLK, MRG_CLK, PCM0_CLK, RES3, + RES4, RES5, RES6, RES7), + PIN(34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, + RES4, RES5, RES6, RES7), + PIN(35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, + RES4, RES5, RES6, RES7), + PIN(36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, + RES4, RES5, RES6, RES7), + PIN(37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, + PWM1, PWM2, CLKM0, RES7), + PIN(38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, + RES4, RES5, CLKM1, RES7), + PIN(39, CM2MCLK, CM2MCLK, CMCSD0, RES3, + RES4, RES5, RES6, DBG_MON_A_17), + PIN(40, CMPCLK, CMPCLK, CMCSK, CMCSD2, + RES4, RES5, RES6, DBG_MON_A_18), + PIN(41, CMMCLK, CMMCLK, RES2, RES3, + RES4, RES5, RES6, DBG_MON_A_19), + PIN(42, DSI_TE, DSI_TE, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(43, SDA2, SDA2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(44, SCL2, SCL2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(45, SDA0, SDA0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(46, SCL0, SCL0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(47, RDN0_A, CMDAT2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(48, RDP0_A, CMDAT3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(49, RDN1_A, CMDAT4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(50, RDP1_A, CMDAT5, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(51, RCN_A, CMDAT6, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(52, RCP_A, CMDAT7, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(53, RDN2_A, CMDAT8, CMCSD3, RES3, + RES4, RES5, RES6, RES7), + PIN(54, RDP2_A, CMDAT9, CMCSD2, RES3, + RES4, RES5, RES6, RES7), + PIN(55, RDN3_A, CMHSYNC, CMCSD1, RES3, + RES4, RES5, RES6, RES7), + PIN(56, RDP3_A, CMVSYNC, CMCSD0, RES3, + RES4, RES5, RES6, RES7), + PIN(57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, + RES4, RES5, RES6, DBG_MON_B_7), + PIN(58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, + RES4, RES5, RES6, DBG_MON_B_8), + PIN(59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, + RES4, RES5, RES6, DBG_MON_B_9), + PIN(60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, + RES4, RES5, RES6, DBG_MON_B_10), + PIN(61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, + RES4, RES5, RES6, DBG_MON_B_11), + PIN(62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, + RES4, RES5, RES6, DBG_MON_B_12), + PIN(63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, + RES4, RES5, RES6, DBG_MON_B_13), + PIN(64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, + RES4, RES5, RES6, DBG_MON_B_14), + PIN(65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_16), + PIN(66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, + RES4, RES5, RES6, DBG_MON_B_15), + PIN(67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_17), + PIN(68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, + RES4, RES5, RES6, DBG_MON_B_18), + PIN(69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, + PWM5, I2S2_MCK, RES6, DBG_MON_B_19), + PIN(70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, + SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20), + PIN(71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, + SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21), + PIN(72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, + PWM6, DISP_PWM1, RES6, DBG_MON_B_22), + PIN(73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_24), + PIN(74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_25), + PIN(75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_26), + PIN(76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_27), + PIN(77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_28), + PIN(78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, + RES4, RES5, RES6, DBG_MON_B_23), + PIN(79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, + RES4, RES5, RES6, RES7), + PIN(80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, + RES4, RES5, RES6, RES7), + PIN(81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, + RES4, RES5, RES6, RES7), + PIN(85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, + RES4, RES5, RES6, RES7), + PIN(86, RTC32K_CK, RTC32K_CK, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, + RES4, RES5, RES6, DBG_MON_B_31), + PIN(88, SRCLKENAI, SRCLKENAI, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(90, SRCLKENA0, SRCLKENA0, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(91, SRCLKENA1, SRCLKENA1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, + RES4, RES5, RES6, DBG_MON_A_24), + PIN(93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, + RES4, RES5, RES6, DBG_MON_A_25), + PIN(94, PCM_RX, PCM1_DI, I2S0_DI, RES3, + RES4, RES5, RES6, DBG_MON_A_26), + PIN(95, PCM_TX, PCM1_DO, I2S0_DO, RES3, + RES4, RES5, RES6, DBG_MON_A_27), + PIN(96, URXD1, URXD1, UTXD1, RES3, + RES4, RES5, RES6, DBG_MON_A_28), + PIN(97, UTXD1, UTXD1, URXD1, RES3, + RES4, RES5, RES6, DBG_MON_A_29), + PIN(98, URTS1, URTS1, UCTS1, RES3, + RES4, RES5, RES6, DBG_MON_A_30), + PIN(99, UCTS1, UCTS1, URTS1, RES3, + RES4, RES5, RES6, DBG_MON_A_31), + PIN(100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, + SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0), + PIN(101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, + SCL5, RES5, RES6, DBG_MON_B_1), + PIN(102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, + RES4, PWM0, SPI_CK_1, DBG_MON_B_2), + PIN(103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, + RES4, PWM1, SPI_MI_1, DBG_MON_B_3), + PIN(104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, + SDA3, PWM2, SPI_MO_1, DBG_MON_B_4), + PIN(105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, + SCL3, PWM3, SPI_CS_1, DBG_MON_B_5), + PIN(106, SDA3, SDA3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(107, SCL3, SCL3, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(108, JTMS, JTMS, MFG_JTAG_TMS, RES3, + RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7), + PIN(109, JTCK, JTCK, MFG_JTAG_TCK, RES3, + RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7), + PIN(110, JTDI, JTDI, MFG_JTAG_TDI, RES3, + RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7), + PIN(111, JTDO, JTDO, MFG_JTAG_TDO, RES3, + RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7), + PIN(112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, + RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7), + PIN(113, URXD0, URXD0, UTXD0, RES3, + RES4, RES5, I2S2_WS, DBG_MON_A_0), + PIN(114, UTXD0, UTXD0, URXD0, RES3, + RES4, RES5, I2S2_BCK, DBG_MON_A_1), + PIN(115, URTS0, URTS0, UCTS0, RES3, + RES4, RES5, I2S2_MCK, DBG_MON_A_2), + PIN(116, UCTS0, UCTS0, URTS0, RES3, + RES4, RES5, I2S2_DI_1, DBG_MON_A_3), + PIN(117, URXD3, URXD3, UTXD3, RES3, + RES4, RES5, RES6, DBG_MON_A_9), + PIN(118, UTXD3, UTXD3, URXD3, RES3, + RES4, RES5, RES6, DBG_MON_A_10), + PIN(119, KPROW0, KROW0, RES2, RES3, + RES4, RES5, RES6, DBG_MON_A_11), + PIN(120, KPROW1, KROW1, RES2, PWM6, + RES4, RES5, RES6, DBG_MON_A_12), + PIN(121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, + PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13), + PIN(122, KPCOL0, KCOL0, RES2, RES3, + RES4, RES5, RES6, DBG_MON_A_14), + PIN(123, KPCOL1, KCOL1, IRDA_RXD, PWM5, + RES4, RES5, RES6, DBG_MON_A_15), + PIN(124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, + PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16), + PIN(125, SDA1, SDA1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(126, SCL1, SCL1, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(127, LCM_RST, LCM_RST, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, + RES4, SPI_CK_2, RES6, DBG_MON_A_4), + PIN(129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, + RES4, SPI_MI_2, RES6, DBG_MON_A_5), + PIN(130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, + RES4, SPI_MO_2, RES6, DBG_MON_A_6), + PIN(131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, + RES4, SPI_CS_2, RES6, DBG_MON_A_7), + PIN(132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, + RES4, RES5, RES6, DBG_MON_A_8), + PIN(133, SDA4, SDA4, RES2, RES3, + RES4, RES5, RES6, RES7), + PIN(134, SCL4, SCL4, RES2, RES3, + RES4, RES5, RES6, RES7), +}; struct val_regs { - uint16_t val; - uint16_t align1; - uint16_t set; - uint16_t align2; - uint16_t rst; - uint16_t align3[3]; + uint32_t val; + uint32_t set; + uint32_t rst; + uint32_t align; }; struct gpio_regs { @@ -80,7 +362,7 @@ struct gpio_regs { check_member(gpio_regs, msdc2_ctrl5, 0xcb0); check_member(gpio_regs, hsic_ctrl[3], 0xe50); -static struct gpio_regs *const mt8173_gpio = (void *)(GPIO_BASE); +static struct gpio_regs *const mtk_gpio = (void *)(GPIO_BASE); void gpio_set_pull(gpio_t gpio, enum pull_enable enable, enum pull_select select); diff --git a/src/soc/mediatek/mt8173/include/soc/pinmux.h b/src/soc/mediatek/mt8173/include/soc/pinmux.h deleted file mode 100644 index 07c53a8380..0000000000 --- a/src/soc/mediatek/mt8173/include/soc/pinmux.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef SOC_MEDIATEK_MT8173_PINMUX_H -#define SOC_MEDIATEK_MT8173_PINMUX_H - -#define PINMUX_CONSTANTS(index, name, func1, func2, func3, func4, func5, func6, func7) \ - PAD_##name = index, \ - PAD_##name##_FUNC_##func1 = 1, \ - PAD_##name##_FUNC_##func2 = 2, \ - PAD_##name##_FUNC_##func3 = 3, \ - PAD_##name##_FUNC_##func4 = 4, \ - PAD_##name##_FUNC_##func5 = 5, \ - PAD_##name##_FUNC_##func6 = 6, \ - PAD_##name##_FUNC_##func7 = 7 - -enum { - PINMUX_CONSTANTS(0, EINT0, IRDA_PDN, I2S1_WS, AUD_SPDIF, UTXD0, RES5, RES6, DBG_MON_A_20), - PINMUX_CONSTANTS(1, EINT1, IRDA_RXD, I2S1_BCK, SDA5, URXD0, RES5, RES6, DBG_MON_A_21), - PINMUX_CONSTANTS(2, EINT2, IRDA_TXD, I2S1_MCK, SCL5, UTXD3, RES5, RES6, DBG_MON_A_22), - PINMUX_CONSTANTS(3, EINT3, DSI1_TE, I2S1_DO_1, SDA3, URXD3, RES5, RES6, DBG_MON_A_23), - PINMUX_CONSTANTS(4, EINT4, DISP_PWM1, I2S1_DO_2, SCL3, UCTS3, RES5, SFWP_B, RES7), - PINMUX_CONSTANTS(5, EINT5, PCM1_CLK, I2S2_WS, SPI_CK_3, URTS3, AP_MD32_JTAG_TMS, SFOUT, RES7), - PINMUX_CONSTANTS(6, EINT6, PCM1_SYNC, I2S2_BCK, SPI_MI_3, RES4, AP_MD32_JTAG_TCK, SFCS0, RES7), - PINMUX_CONSTANTS(7, EINT7, PCM1_DI, I2S2_DI_1, SPI_MO_3, RES4, AP_MD32_JTAG_TDI, SFHOLD, RES7), - PINMUX_CONSTANTS(8, EINT8, PCM1_DO, I2S2_DI_2, SPI_CS_3, AUD_SPDIF, AP_MD32_JTAG_TDO, SFIN, RES7), - PINMUX_CONSTANTS(9, EINT9, USB_DRVVBUS_P0, I2S2_MCK, RES3, USB_DRVVBUS_P1, AP_MD32_JTAG_TRST, SFCK, RES7), - PINMUX_CONSTANTS(10, EINT10, CLKM0, DSI1_TE, DISP_PWM1, PWM4, IRDA_RXD, RES6, RES7), - PINMUX_CONSTANTS(11, EINT11, CLKM1, I2S3_WS, USB_DRVVBUS_P0, PWM5, IRDA_TXD, USB_DRVVBUS_P1, DBG_MON_B_30), - PINMUX_CONSTANTS(12, EINT12, CLKM2, I2S3_BCK, SRCLKENA0, RES4, I2S2_WS, RES6, DBG_MON_B_32), - PINMUX_CONSTANTS(13, EINT13, CLKM3, I2S3_MCK, SRCLKENA0, RES4, I2S2_BCK, RES6, DBG_MON_A_32), - PINMUX_CONSTANTS(14, EINT14, CMDAT0, CMCSD0, RES3, CLKM2, RES5, RES6, DBG_MON_B_6), - PINMUX_CONSTANTS(15, EINT15, CMDAT1, CMCSD1, CMFLASH, CLKM3, RES5, RES6, DBG_MON_B_29), - PINMUX_CONSTANTS(16, IDDIG, IDDIG, CMFLASH, RES3, PWM5, RES5, RES6, RES7), - PINMUX_CONSTANTS(17, WATCHDOG, WATCHDOG_AO, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(18, CEC, CEC, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(19, HDMISCK, HDMISCK, HDCP_SCL, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(20, HDMISD, HDMISD, HDCP_SDA, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(21, HTPLG, HTPLG, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(22, MSDC3_DAT0, MSDC3_DAT0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(23, MSDC3_DAT1, MSDC3_DAT1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(24, MSDC3_DAT2, MSDC3_DAT2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(25, MSDC3_DAT3, MSDC3_DAT3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(26, MSDC3_CLK, MSDC3_CLK, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(27, MSDC3_CMD, MSDC3_CMD, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(28, MSDC3_DSL, MSDC3_DSL, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(29, UCTS2, UCTS2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(30, URTS2, URTS2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(31, URXD2, URXD2, UTXD2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(32, UTXD2, UTXD2, URXD2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(33, DAICLK, MRG_CLK, PCM0_CLK, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(34, DAIPCMIN, MRG_DI, PCM0_DI, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(35, DAIPCMOUT, MRG_DO, PCM0_DO, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(36, DAISYNC, MRG_SYNC, PCM0_SYNC, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(37, EINT16, USB_DRVVBUS_P0, USB_DRVVBUS_P1, PWM0, PWM1, PWM2, CLKM0, RES7), - PINMUX_CONSTANTS(38, CONN_RST, USB_DRVVBUS_P0, USB_DRVVBUS_P1, RES3, RES4, RES5, CLKM1, RES7), - PINMUX_CONSTANTS(39, CM2MCLK, CM2MCLK, CMCSD0, RES3, RES4, RES5, RES6, DBG_MON_A_17), - PINMUX_CONSTANTS(40, CMPCLK, CMPCLK, CMCSK, CMCSD2, RES4, RES5, RES6, DBG_MON_A_18), - PINMUX_CONSTANTS(41, CMMCLK, CMMCLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_19), - PINMUX_CONSTANTS(42, DSI_TE, DSI_TE, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(43, SDA2, SDA2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(44, SCL2, SCL2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(45, SDA0, SDA0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(46, SCL0, SCL0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(47, RDN0_A, CMDAT2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(48, RDP0_A, CMDAT3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(49, RDN1_A, CMDAT4, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(50, RDP1_A, CMDAT5, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(51, RCN_A, CMDAT6, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(52, RCP_A, CMDAT7, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(53, RDN2_A, CMDAT8, CMCSD3, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(54, RDP2_A, CMDAT9, CMCSD2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(55, RDN3_A, CMHSYNC, CMCSD1, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(56, RDP3_A, CMVSYNC, CMCSD0, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(57, MSDC0_DAT0, MSDC0_DAT0, I2S1_WS, RES3, RES4, RES5, RES6, DBG_MON_B_7), - PINMUX_CONSTANTS(58, MSDC0_DAT1, MSDC0_DAT1, I2S1_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_8), - PINMUX_CONSTANTS(59, MSDC0_DAT2, MSDC0_DAT2, I2S1_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_9), - PINMUX_CONSTANTS(60, MSDC0_DAT3, MSDC0_DAT3, I2S1_DO_1, RES3, RES4, RES5, RES6, DBG_MON_B_10), - PINMUX_CONSTANTS(61, MSDC0_DAT4, MSDC0_DAT4, I2S1_DO_2, RES3, RES4, RES5, RES6, DBG_MON_B_11), - PINMUX_CONSTANTS(62, MSDC0_DAT5, MSDC0_DAT5, I2S2_WS, RES3, RES4, RES5, RES6, DBG_MON_B_12), - PINMUX_CONSTANTS(63, MSDC0_DAT6, MSDC0_DAT6, I2S2_BCK, RES3, RES4, RES5, RES6, DBG_MON_B_13), - PINMUX_CONSTANTS(64, MSDC0_DAT7, MSDC0_DAT7, I2S2_DI_1, RES3, RES4, RES5, RES6, DBG_MON_B_14), - PINMUX_CONSTANTS(65, MSDC0_CLK, MSDC0_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_16), - PINMUX_CONSTANTS(66, MSDC0_CMD, MSDC0_CMD, I2S2_DI_2, RES3, RES4, RES5, RES6, DBG_MON_B_15), - PINMUX_CONSTANTS(67, MSDC0_DSL, MSDC0_DSL, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_17), - PINMUX_CONSTANTS(68, MSDC0_RST, MSDC0_RSTB, I2S2_MCK, RES3, RES4, RES5, RES6, DBG_MON_B_18), - PINMUX_CONSTANTS(69, SPI_CK, SPI_CK_0, I2S3_DO_1, PWM0, PWM5, I2S2_MCK, RES6, DBG_MON_B_19), - PINMUX_CONSTANTS(70, SPI_MI, SPI_MI_0, I2S3_DO_2, PWM1, SPI_MO_0, I2S2_DI_1, DSI1_TE, DBG_MON_B_20), - PINMUX_CONSTANTS(71, SPI_MO, SPI_MO_0, I2S3_DO_3, PWM2, SPI_MI_0, I2S2_DI_2, RES6, DBG_MON_B_21), - PINMUX_CONSTANTS(72, SPI_CS, SPI_CS_0, I2S3_DO_4, PWM3, PWM6, DISP_PWM1, RES6, DBG_MON_B_22), - PINMUX_CONSTANTS(73, MSDC1_DAT0, MSDC1_DAT0, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_24), - PINMUX_CONSTANTS(74, MSDC1_DAT1, MSDC1_DAT1, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_25), - PINMUX_CONSTANTS(75, MSDC1_DAT2, MSDC1_DAT2, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_26), - PINMUX_CONSTANTS(76, MSDC1_DAT3, MSDC1_DAT3, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_27), - PINMUX_CONSTANTS(77, MSDC1_CLK, MSDC1_CLK, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_28), - PINMUX_CONSTANTS(78, MSDC1_CMD, MSDC1_CMD, RES2, RES3, RES4, RES5, RES6, DBG_MON_B_23), - PINMUX_CONSTANTS(79, PWRAP_SPI0_MI, PWRAP_SPIMI, PWRAP_SPIMO, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(80, PWRAP_SPI0_MO, PWRAP_SPIMO, PWRAP_SPIMI, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(81, PWRAP_SPI0_CK, PWRAP_SPICK, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(82, PWRAP_SPI0_CSN, PWRAP_SPICS, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(83, AUD_CLK_MOSI, AUD_CLK_MOSI, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(84, AUD_DAT_MISO, AUD_DAT_MISO, AUD_DAT_MOSI, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(85, AUD_DAT_MOSI, AUD_DAT_MOSI, AUD_DAT_MISO, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(86, RTC32K_CK, RTC32K_CK, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(87, DISP_PWM0, DISP_PWM0, DISP_PWM1, RES3, RES4, RES5, RES6, DBG_MON_B_31), - PINMUX_CONSTANTS(88, SRCLKENAI, SRCLKENAI, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(89, SRCLKENAI2, SRCLKENAI2, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(90, SRCLKENA0, SRCLKENA0, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(91, SRCLKENA1, SRCLKENA1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(92, PCM_CLK, PCM1_CLK, I2S0_BCK, RES3, RES4, RES5, RES6, DBG_MON_A_24), - PINMUX_CONSTANTS(93, PCM_SYNC, PCM1_SYNC, I2S0_WS, RES3, RES4, RES5, RES6, DBG_MON_A_25), - PINMUX_CONSTANTS(94, PCM_RX, PCM1_DI, I2S0_DI, RES3, RES4, RES5, RES6, DBG_MON_A_26), - PINMUX_CONSTANTS(95, PCM_TX, PCM1_DO, I2S0_DO, RES3, RES4, RES5, RES6, DBG_MON_A_27), - PINMUX_CONSTANTS(96, URXD1, URXD1, UTXD1, RES3, RES4, RES5, RES6, DBG_MON_A_28), - PINMUX_CONSTANTS(97, UTXD1, UTXD1, URXD1, RES3, RES4, RES5, RES6, DBG_MON_A_29), - PINMUX_CONSTANTS(98, URTS1, URTS1, UCTS1, RES3, RES4, RES5, RES6, DBG_MON_A_30), - PINMUX_CONSTANTS(99, UCTS1, UCTS1, URTS1, RES3, RES4, RES5, RES6, DBG_MON_A_31), - PINMUX_CONSTANTS(100, MSDC2_DAT0, MSDC2_DAT0, RES2, USB_DRVVBUS_P0, SDA5, USB_DRVVBUS_P1, RES6, DBG_MON_B_0), - PINMUX_CONSTANTS(101, MSDC2_DAT1, MSDC2_DAT1, RES2, AUD_SPDIF, SCL5, RES5, RES6, DBG_MON_B_1), - PINMUX_CONSTANTS(102, MSDC2_DAT2, MSDC2_DAT2, RES2, UTXD0, RES4, PWM0, SPI_CK_1, DBG_MON_B_2), - PINMUX_CONSTANTS(103, MSDC2_DAT3, MSDC2_DAT3, RES2, URXD0, RES4, PWM1, SPI_MI_1, DBG_MON_B_3), - PINMUX_CONSTANTS(104, MSDC2_CLK, MSDC2_CLK, RES2, UTXD3, SDA3, PWM2, SPI_MO_1, DBG_MON_B_4), - PINMUX_CONSTANTS(105, MSDC2_CMD, MSDC2_CMD, RES2, URXD3, SCL3, PWM3, SPI_CS_1, DBG_MON_B_5), - PINMUX_CONSTANTS(106, SDA3, SDA3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(107, SCL3, SCL3, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(108, JTMS, JTMS, MFG_JTAG_TMS, RES3, RES4, AP_MD32_JTAG_TMS, DFD_TMS, RES7), - PINMUX_CONSTANTS(109, JTCK, JTCK, MFG_JTAG_TCK, RES3, RES4, AP_MD32_JTAG_TCK, DFD_TCK, RES7), - PINMUX_CONSTANTS(110, JTDI, JTDI, MFG_JTAG_TDI, RES3, RES4, AP_MD32_JTAG_TDI, DFD_TDI, RES7), - PINMUX_CONSTANTS(111, JTDO, JTDO, MFG_JTAG_TDO, RES3, RES4, AP_MD32_JTAG_TDO, DFD_TDO, RES7), - PINMUX_CONSTANTS(112, JTRST_B, JTRST_B, MFG_JTAG_TRSTN, RES3, RES4, AP_MD32_JTAG_TRST, DFD_NTRST, RES7), - PINMUX_CONSTANTS(113, URXD0, URXD0, UTXD0, RES3, RES4, RES5, I2S2_WS, DBG_MON_A_0), - PINMUX_CONSTANTS(114, UTXD0, UTXD0, URXD0, RES3, RES4, RES5, I2S2_BCK, DBG_MON_A_1), - PINMUX_CONSTANTS(115, URTS0, URTS0, UCTS0, RES3, RES4, RES5, I2S2_MCK, DBG_MON_A_2), - PINMUX_CONSTANTS(116, UCTS0, UCTS0, URTS0, RES3, RES4, RES5, I2S2_DI_1, DBG_MON_A_3), - PINMUX_CONSTANTS(117, URXD3, URXD3, UTXD3, RES3, RES4, RES5, RES6, DBG_MON_A_9), - PINMUX_CONSTANTS(118, UTXD3, UTXD3, URXD3, RES3, RES4, RES5, RES6, DBG_MON_A_10), - PINMUX_CONSTANTS(119, KPROW0, KROW0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_11), - PINMUX_CONSTANTS(120, KPROW1, KROW1, RES2, PWM6, RES4, RES5, RES6, DBG_MON_A_12), - PINMUX_CONSTANTS(121, KPROW2, KROW2, IRDA_PDN, USB_DRVVBUS_P0, PWM4, USB_DRVVBUS_P1, RES6, DBG_MON_A_13), - PINMUX_CONSTANTS(122, KPCOL0, KCOL0, RES2, RES3, RES4, RES5, RES6, DBG_MON_A_14), - PINMUX_CONSTANTS(123, KPCOL1, KCOL1, IRDA_RXD, PWM5, RES4, RES5, RES6, DBG_MON_A_15), - PINMUX_CONSTANTS(124, KPCOL2, KCOL2, IRDA_TXD, USB_DRVVBUS_P0, PWM3, USB_DRVVBUS_P1, RES6, DBG_MON_A_16), - PINMUX_CONSTANTS(125, SDA1, SDA1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(126, SCL1, SCL1, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(127, LCM_RST, LCM_RST, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(128, I2S0_LRCK, I2S0_WS, I2S1_WS, I2S2_WS, RES4, SPI_CK_2, RES6, DBG_MON_A_4), - PINMUX_CONSTANTS(129, I2S0_BCK, I2S0_BCK, I2S1_BCK, I2S2_BCK, RES4, SPI_MI_2, RES6, DBG_MON_A_5), - PINMUX_CONSTANTS(130, I2S0_MCK, I2S0_MCK, I2S1_MCK, I2S2_MCK, RES4, SPI_MO_2, RES6, DBG_MON_A_6), - PINMUX_CONSTANTS(131, I2S0_DATA0, I2S0_DO, I2S1_DO_1, I2S2_DI_1, RES4, SPI_CS_2, RES6, DBG_MON_A_7), - PINMUX_CONSTANTS(132, I2S0_DATA1, I2S0_DI, I2S1_DO_2, I2S2_DI_2, RES4, RES5, RES6, DBG_MON_A_8), - PINMUX_CONSTANTS(133, SDA4, SDA4, RES2, RES3, RES4, RES5, RES6, RES7), - PINMUX_CONSTANTS(134, SCL4, SCL4, RES2, RES3, RES4, RES5, RES6, RES7), -}; - -#endif /* SOC_MEDIATEK_MT8173_PINMUX_H */ diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index f70f4d991e..b15685a352 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -25,7 +25,6 @@ #include <soc/addressmap.h> #include <soc/flash_controller.h> #include <soc/gpio.h> -#include <soc/pinmux.h> #include <soc/pll.h> #include <soc/spi.h> @@ -68,10 +67,10 @@ static void mtk_spi_set_gpio_pinmux(enum spi_pad_mask pad_select) { /* TODO: implement support for other pads when needed */ assert(pad_select == SPI_PAD1_MASK); - gpio_set_mode(PAD_MSDC2_DAT2, PAD_MSDC2_DAT2_FUNC_SPI_CK_1); - gpio_set_mode(PAD_MSDC2_DAT3, PAD_MSDC2_DAT3_FUNC_SPI_MI_1); - gpio_set_mode(PAD_MSDC2_CLK, PAD_MSDC2_CLK_FUNC_SPI_MO_1); - gpio_set_mode(PAD_MSDC2_CMD, PAD_MSDC2_CMD_FUNC_SPI_CS_1); + gpio_set_mode(GPIO(MSDC2_DAT2), PAD_MSDC2_DAT2_FUNC_SPI_CK_1); + gpio_set_mode(GPIO(MSDC2_DAT3), PAD_MSDC2_DAT3_FUNC_SPI_MI_1); + gpio_set_mode(GPIO(MSDC2_CLK), PAD_MSDC2_CLK_FUNC_SPI_MO_1); + gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1); } void mtk_spi_init(unsigned int bus, unsigned int pad_select, |