diff options
Diffstat (limited to 'src/soc/mediatek/mt8173/pmic_wrap.c')
-rw-r--r-- | src/soc/mediatek/mt8173/pmic_wrap.c | 277 |
1 files changed, 33 insertions, 244 deletions
diff --git a/src/soc/mediatek/mt8173/pmic_wrap.c b/src/soc/mediatek/mt8173/pmic_wrap.c index d7d4193c8a..2c60e76cbd 100644 --- a/src/soc/mediatek/mt8173/pmic_wrap.c +++ b/src/soc/mediatek/mt8173/pmic_wrap.c @@ -15,183 +15,10 @@ #include <arch/io.h> #include <assert.h> -#include <console/console.h> #include <delay.h> #include <soc/infracfg.h> #include <soc/pmic_wrap.h> -#include <timer.h> -#define PWRAPTAG "[PWRAP] " -#define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg) -#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \ - __LINE__, ## arg) - -/* define macro and inline function (for do while loop) */ - -typedef u32 (*loop_condition_fp)(u32); - -static inline u32 wait_for_fsm_vldclr(u32 x) -{ - return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != - WACS_FSM_WFVLDCLR; -} - -static inline u32 wait_for_sync(u32 x) -{ - return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) != - WACS_SYNC_IDLE; -} - -static inline u32 wait_for_idle_and_sync(u32 x) -{ - return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != - WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) & - RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE)); -} - -static inline u32 wait_for_cipher_ready(u32 x) -{ - return x != 3; -} - -static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register, - void *wacs_vldclr_register, - u32 *read_reg) -{ - u32 reg_rdata; - - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, timeout_us); - do { - reg_rdata = read32((wacs_register)); - /* if last read command timeout,clear vldclr bit - read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; - write:FSM_REQ-->idle */ - switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & - RDATA_WACS_FSM_MASK)) { - case WACS_FSM_WFVLDCLR: - write32(wacs_vldclr_register, 1); - pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); - break; - case WACS_FSM_WFDLE: - pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n"); - break; - case WACS_FSM_REQ: - pwrap_err("WACS_FSM = WACS_FSM_REQ\n"); - break; - default: - break; - } - - if (stopwatch_expired(&sw)) - return E_PWR_WAIT_IDLE_TIMEOUT; - - } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != - WACS_FSM_IDLE); /* IDLE State */ - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us, - void *wacs_register, u32 *read_reg) -{ - u32 reg_rdata; - struct stopwatch sw; - - stopwatch_init_usecs_expire(&sw, timeout_us); - do { - reg_rdata = read32((wacs_register)); - - if (stopwatch_expired(&sw)) { - pwrap_err("timeout when waiting for idle\n"); - return E_PWR_WAIT_IDLE_TIMEOUT; - } - } while (fp(reg_rdata)); /* IDLE State */ - if (read_reg) - *read_reg = reg_rdata; - return 0; -} - -s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check) -{ - u32 reg_rdata = 0; - u32 wacs_write = 0; - u32 wacs_adr = 0; - u32 wacs_cmd = 0; - u32 return_value = 0; - - if (init_check) { - reg_rdata = read32(&mt8173_pwrap->wacs2_rdata); - /* Prevent someone to used pwrap before pwrap init */ - if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & - RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { - pwrap_err("initialization isn't finished\n"); - return E_PWR_NOT_INIT_DONE; - } - } - reg_rdata = 0; - /* Check IDLE in advance */ - return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US, - &mt8173_pwrap->wacs2_rdata, - &mt8173_pwrap->wacs2_vldclr, - 0); - if (return_value != 0) { - pwrap_err("wait_for_fsm_idle fail,return_value=%d\n", - return_value); - return E_PWR_WAIT_IDLE_TIMEOUT; - } - wacs_write = write << 31; - wacs_adr = (adr >> 1) << 16; - wacs_cmd = wacs_write | wacs_adr | wdata; - - write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd); - if (write == 0) { - if (NULL == rdata) { - pwrap_err("rdata is a NULL pointer\n"); - return E_PWR_INVALID_ARG; - } - return_value = wait_for_state_ready(wait_for_fsm_vldclr, - TIMEOUT_READ_US, - &mt8173_pwrap->wacs2_rdata, - ®_rdata); - if (return_value != 0) { - pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n", - return_value); - return E_PWR_WAIT_IDLE_TIMEOUT_READ; - } - *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) - & RDATA_WACS_RDATA_MASK); - write32(&mt8173_pwrap->wacs2_vldclr, 1); - } - - return 0; -} - -/* external API for pmic_wrap user */ - -s32 pwrap_read(u16 adr, u16 *rdata) -{ - return pwrap_wacs2(0, adr, 0, rdata, 1); -} - -s32 pwrap_write(u16 adr, u16 wdata) -{ - return pwrap_wacs2(1, adr, wdata, 0, 1); -} - -static s32 pwrap_read_nochk(u16 adr, u16 *rdata) -{ - return pwrap_wacs2(0, adr, 0, rdata, 0); -} - -static s32 pwrap_write_nochk(u16 adr, u16 wdata) -{ - return pwrap_wacs2(1, adr, wdata, 0, 0); -} - -/* call it in pwrap_init,mustn't check init done */ static s32 pwrap_init_dio(u32 dio_en) { u16 rdata = 0; @@ -203,13 +30,13 @@ static s32 pwrap_init_dio(u32 dio_en) return_value = wait_for_state_ready(wait_for_idle_and_sync, TIMEOUT_WAIT_IDLE_US, - &mt8173_pwrap->wacs2_rdata, + &mtk_pwrap->wacs2_rdata, 0); if (return_value != 0) { pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); return return_value; } - write32(&mt8173_pwrap->dio_en, dio_en); + write32(&mtk_pwrap->dio_en, dio_en); /* Read Test */ pwrap_read_nochk(DEW_READ_TEST, &rdata); if (rdata != DEFAULT_VALUE_READ_TEST) { @@ -235,7 +62,7 @@ static s32 pwrap_init_sidly(void) u32 sidly = 0; for (i = 0; i < 4; i++) { - write32(&mt8173_pwrap->sidly, i); + write32(&mtk_pwrap->sidly, i); pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0); if (rdata == DEFAULT_VALUE_READ_TEST) pass |= 1 << i; @@ -285,49 +112,11 @@ static s32 pwrap_init_sidly(void) die("sidly pass range not continuous\n"); } - write32(&mt8173_pwrap->sidly, sidly); + write32(&mtk_pwrap->sidly, sidly); return 0; } -static s32 pwrap_reset_spislv(void) -{ - u32 ret = 0; - u32 return_value = 0; - - write32(&mt8173_pwrap->hiprio_arb_en, 0); - write32(&mt8173_pwrap->wrap_en, 0); - write32(&mt8173_pwrap->mux_sel, 1); - write32(&mt8173_pwrap->man_en, 1); - write32(&mt8173_pwrap->dio_en, 0); - - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8)); - /* to reset counter */ - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8)); - /* - * In order to pull CSN signal to PMIC, - * PMIC will count it then reset spi slave - */ - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); - - return_value = wait_for_state_ready(wait_for_sync, - TIMEOUT_WAIT_IDLE_US, - &mt8173_pwrap->wacs2_rdata, 0); - if (return_value != 0) { - pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); - ret = E_PWR_TIMEOUT; - } - - write32(&mt8173_pwrap->man_en, 0); - write32(&mt8173_pwrap->mux_sel, 0); - - return ret; -} - static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel) { u16 wdata = 0; @@ -350,25 +139,25 @@ static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel) /* Config SPI Waveform according to reg clk */ switch (regck_sel) { case REG_CLOCK_18MHZ: - write32(&mt8173_pwrap->rddmy, 0xc); - write32(&mt8173_pwrap->cshext_write, 0x0); - write32(&mt8173_pwrap->cshext_read, 0x4); - write32(&mt8173_pwrap->cslext_start, 0x0); - write32(&mt8173_pwrap->cslext_end, 0x4); + write32(&mtk_pwrap->rddmy, 0xc); + write32(&mtk_pwrap->cshext_write, 0x0); + write32(&mtk_pwrap->cshext_read, 0x4); + write32(&mtk_pwrap->cslext_start, 0x0); + write32(&mtk_pwrap->cslext_end, 0x4); break; case REG_CLOCK_26MHZ: - write32(&mt8173_pwrap->rddmy, 0xc); - write32(&mt8173_pwrap->cshext_write, 0x0); - write32(&mt8173_pwrap->cshext_read, 0x4); - write32(&mt8173_pwrap->cslext_start, 0x2); - write32(&mt8173_pwrap->cslext_end, 0x2); + write32(&mtk_pwrap->rddmy, 0xc); + write32(&mtk_pwrap->cshext_write, 0x0); + write32(&mtk_pwrap->cshext_read, 0x4); + write32(&mtk_pwrap->cslext_start, 0x2); + write32(&mtk_pwrap->cslext_end, 0x2); break; default: - write32(&mt8173_pwrap->rddmy, 0xf); - write32(&mt8173_pwrap->cshext_write, 0xf); - write32(&mt8173_pwrap->cshext_read, 0xf); - write32(&mt8173_pwrap->cslext_start, 0xf); - write32(&mt8173_pwrap->cslext_end, 0xf); + write32(&mtk_pwrap->rddmy, 0xf); + write32(&mtk_pwrap->cshext_write, 0xf); + write32(&mtk_pwrap->cshext_read, 0xf); + write32(&mtk_pwrap->cslext_start, 0xf); + write32(&mtk_pwrap->cslext_end, 0xf); break; } @@ -388,8 +177,8 @@ s32 pwrap_init(void) clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); /* Enable DCM */ - write32(&mt8173_pwrap->dcm_en, 3); - write32(&mt8173_pwrap->dcm_dbc_prd, 0); + write32(&mtk_pwrap->dcm_en, 3); + write32(&mtk_pwrap->dcm_dbc_prd, 0); /* Reset SPISLV */ sub_return = pwrap_reset_spislv(); @@ -399,9 +188,9 @@ s32 pwrap_init(void) return E_PWR_INIT_RESET_SPI; } /* Enable WACS2 */ - write32(&mt8173_pwrap->wrap_en, 1); - write32(&mt8173_pwrap->hiprio_arb_en, WACS2); - write32(&mt8173_pwrap->wacs2_en, 1); + write32(&mtk_pwrap->wrap_en, 1); + write32(&mtk_pwrap->hiprio_arb_en, WACS2); + write32(&mtk_pwrap->wacs2_en, 1); /* SIDLY setting */ sub_return = pwrap_init_sidly(); @@ -461,14 +250,14 @@ s32 pwrap_init(void) pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return); return E_PWR_INIT_ENABLE_CRC; } - write32(&mt8173_pwrap->crc_en, 0x1); - write32(&mt8173_pwrap->sig_mode, 0x0); - write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL); + write32(&mtk_pwrap->crc_en, 0x1); + write32(&mtk_pwrap->sig_mode, 0x0); + write32(&mtk_pwrap->sig_adr, DEW_CRC_VAL); /* PMIC_WRAP enables */ - write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff); - write32(&mt8173_pwrap->wacs0_en, 0x1); - write32(&mt8173_pwrap->wacs1_en, 0x1); + write32(&mtk_pwrap->hiprio_arb_en, 0x1ff); + write32(&mtk_pwrap->wacs0_en, 0x1); + write32(&mtk_pwrap->wacs1_en, 0x1); /* * switch event pin from usbdl mode to normal mode for pmic interrupt, @@ -481,9 +270,9 @@ s32 pwrap_init(void) sub_return); /* Initialization Done */ - write32(&mt8173_pwrap->init_done2, 0x1); - write32(&mt8173_pwrap->init_done0, 0x1); - write32(&mt8173_pwrap->init_done1, 0x1); + write32(&mtk_pwrap->init_done2, 0x1); + write32(&mtk_pwrap->init_done0, 0x1); + write32(&mtk_pwrap->init_done1, 0x1); return 0; } |