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-rw-r--r--src/soc/intel/apollolake/chip.c5
-rw-r--r--src/soc/intel/apollolake/cpu.c2
2 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 1dd6daf16c..cac2c0061c 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -565,9 +565,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable;
/* Disable monitor mwait since it is broken due to a hardware bug
- * without a fix
+ * without a fix. Specific to Apollolake.
*/
- silconfig->MonitorMwaitEnable = 0;
+ if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK))
+ silconfig->MonitorMwaitEnable = 0;
silconfig->SkipMpInit = 1;
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index d093acc06a..172a2b9708 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -45,6 +45,7 @@
#include <soc/pm.h>
static const struct reg_script core_msr_script[] = {
+#if !IS_ENABLED(CONFIG_SOC_INTEL_GLK)
/* Enable C-state and IO/MWAIT redirect */
REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL,
(PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK
@@ -56,6 +57,7 @@ static const struct reg_script core_msr_script[] = {
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
/* Disable support for MONITOR and MWAIT instructions */
REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),
+#endif
/*
* Enable and Lock the Advanced Encryption Standard (AES-NI)
* feature register