summaryrefslogtreecommitdiff
path: root/src/soc/intel
diff options
context:
space:
mode:
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/systemagent/Kconfig4
-rw-r--r--src/soc/intel/denverton_ns/Kconfig4
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig
index 1222573201..6dd1f3b363 100644
--- a/src/soc/intel/common/block/systemagent/Kconfig
+++ b/src/soc/intel/common/block/systemagent/Kconfig
@@ -3,6 +3,8 @@ config SOC_INTEL_COMMON_BLOCK_SA
help
Intel Processor common System Agent support
+if SOC_INTEL_COMMON_BLOCK_SA
+
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
@@ -36,3 +38,5 @@ config SA_ENABLE_DPR
default n
help
This option allows you to add the DMA Protected Range (DPR).
+
+endif
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index fa49eb0d9a..aed2beb3fd 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -54,6 +54,10 @@ config CPU_SPECIFIC_OPTIONS
select UDK_2015_BINDING
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
config FSP_T_ADDR
hex "Intel FSP-T (temp ram init) binary location"
depends on ADD_FSP_BINARIES && FSP_CAR