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-rw-r--r--src/soc/intel/alderlake/include/soc/meminit.h4
-rw-r--r--src/soc/intel/alderlake/meminit.c3
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h
index bd75636e9b..1d9eaf9414 100644
--- a/src/soc/intel/alderlake/include/soc/meminit.h
+++ b/src/soc/intel/alderlake/include/soc/meminit.h
@@ -107,6 +107,10 @@ struct mb_cfg {
/* Enable/Disable TxDqDqs Retraining for Lp4/Lp5/DDR */
uint8_t LpDdrDqDqsReTraining;
+
+ /* Enable/Disable Cs Pi Start with High value in Ect */
+ uint8_t cs_pi_start_high_in_ect;
+
};
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c
index 862a322a53..2e64e773f8 100644
--- a/src/soc/intel/alderlake/meminit.c
+++ b/src/soc/intel/alderlake/meminit.c
@@ -240,6 +240,9 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
bool dq_dqs_auto_detect = false;
FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig;
+#if CONFIG(SOC_INTEL_RAPTORLAKE)
+ mem_cfg->CsPiStartHighinEct = mb_cfg->cs_pi_start_high_in_ect;
+#endif
mem_cfg->ECT = mb_cfg->ect;
mem_cfg->UserBd = mb_cfg->UserBd;
set_rcomp_config(mem_cfg, mb_cfg);