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-rw-r--r--src/soc/intel/xeon_sp/include/soc/ddr.h1
-rw-r--r--src/soc/intel/xeon_sp/spr/romstage.c3
2 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/ddr.h b/src/soc/intel/xeon_sp/include/soc/ddr.h
index bb10caaf1f..0b5bdb6b15 100644
--- a/src/soc/intel/xeon_sp/include/soc/ddr.h
+++ b/src/soc/intel/xeon_sp/include/soc/ddr.h
@@ -9,7 +9,6 @@
* currently DDR4 only supports 1.2V, DDR5 only supports 1.1V. */
#define SPD_VDD_DDR4 3
#define SPD_VDD_DDR5 0
-#define SPD_TYPE_DDR5 0x12
/* DDR_*_TCK_MIN are in picoseconds */
#define DDR_800_TCK_MIN 2500
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index bdb9886a8d..c339506573 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -13,6 +13,7 @@
#include <fsp/util.h>
#include <hob_iiouds.h>
#include <hob_memmap.h>
+#include <spd.h>
#include <soc/chip_common.h>
#include <soc/romstage.h>
#include <soc/pci_devs.h>
@@ -330,7 +331,7 @@ void save_dimm_info(void)
dest_dimm->soc_num = soc;
- if (hob->DramType == SPD_TYPE_DDR5) {
+ if (hob->DramType == SPD_MEMORY_TYPE_DDR5_SDRAM) {
/* hard-coded memory device type as DDR5 */
mem_dev_type = 0x22;
data_width = 64;