diff options
Diffstat (limited to 'src/soc/intel')
4 files changed, 21 insertions, 21 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h index d0c81808c8..4788f7a0fb 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v1.h @@ -13,8 +13,8 @@ enum cse_boot_perf_data_v1 { /* CSME ROM completed execution / CSME RBE started */ PERF_DATA_CSME_ROM_COMPLETED = 2, - /* CSME got ESE Init Done indication from ESE */ - PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, + /* CSME got ISSE Init Done indication from ISSE */ + PERF_DATA_CSME_GOT_ISSE_INIT_DONE = 3, /* CSME RBE start PMC patch/es loading */ PERF_DATA_CSME_RBE_PMC_PATCH_LOADING_START = 4, diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h index 4acdc31f16..67eb36bfa4 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v2.h @@ -13,8 +13,8 @@ enum cse_boot_perf_data_v2 { /* CSME ROM completed execution / CSME RBE started */ PERF_DATA_CSME_ROM_COMPLETED = 2, - /* CSME got ESE Init Done indication from ESE */ - PERF_DATA_CSME_GOT_ESE_INIT_DONE = 3, + /* CSME got ISSE Init Done indication from ISSE */ + PERF_DATA_CSME_GOT_ISSE_INIT_DONE = 3, /* CSME RBE started SOC.PMC patch and payloads read from SPI flash */ PERF_DATA_CSME_RBE_SOC_PMC_PATCH_LOADING_START = 4, @@ -43,11 +43,11 @@ enum cse_boot_perf_data_v2 { /* CSME BUP start running */ PERF_DATA_CSME_BUP_START = 12, - /* CSME established IPC channel communication with ESE */ - PERF_DATA_CSME_IPC_CHANNEL_FOR_ESE_UP = 13, + /* CSME established IPC channel communication with ISSE */ + PERF_DATA_CSME_IPC_CHANNEL_FOR_ISSE_UP = 13, - /* ESE FW initialization completed */ - PERF_DATA_ESE_FW_INIT_DONE = 14, + /* ISSE FW initialization completed */ + PERF_DATA_ISSE_FW_INIT_DONE = 14, /* PMC set PPS */ PERF_DATA_PMC_SET_PPS = 15, @@ -73,8 +73,8 @@ enum cse_boot_perf_data_v2 { /* PMC indicated CSME that SYS_PWROK was asserted */ PERF_DATA_PMC_SYS_PWROK_ASSERTED = 22, - /* ESE sent IPC message to CSME indicating PUnit load completed */ - PERF_DATA_ESE_PUNIT_LOAD_COMPLETED = 23, + /* ISSE sent IPC message to CSME indicating PUnit load completed */ + PERF_DATA_ISSE_PUNIT_LOAD_COMPLETED = 23, /* PMC indicates CSME that xxPLTRST was de-asserted */ PERF_DATA_PMC_PLTRST_DEASSERTED = 24, @@ -94,8 +94,8 @@ enum cse_boot_perf_data_v2 { /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ PERF_DATA_PMC_SENT_CRDA = 29, - /* ESE sent IPC message to CSME indicating DMU load completed */ - PERF_DATA_ESE_DMU_LOAD_COMPLETED = 30, + /* ISSE sent IPC message to CSME indicating DMU load completed */ + PERF_DATA_ISSE_DMU_LOAD_COMPLETED = 30, /* ACM Active indication - ACM started its execution */ PERF_DATA_ACM_START = 31, diff --git a/src/soc/intel/meteorlake/cse_telemetry.c b/src/soc/intel/meteorlake/cse_telemetry.c index 7f5d947a28..6a599c9306 100644 --- a/src/soc/intel/meteorlake/cse_telemetry.c +++ b/src/soc/intel/meteorlake/cse_telemetry.c @@ -24,6 +24,6 @@ void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); - timestamp_add(TS_ESE_DMU_LOAD_END, - start_stamp + ts[PERF_DATA_ESE_DMU_LOAD_COMPLETED]); + timestamp_add(TS_ISSE_DMU_LOAD_END, + start_stamp + ts[PERF_DATA_ISSE_DMU_LOAD_COMPLETED]); } diff --git a/src/soc/intel/meteorlake/include/soc/pci_devs.h b/src/soc/intel/meteorlake/include/soc/pci_devs.h index 10d8bdec42..f52ca6edaa 100644 --- a/src/soc/intel/meteorlake/include/soc/pci_devs.h +++ b/src/soc/intel/meteorlake/include/soc/pci_devs.h @@ -144,13 +144,13 @@ #define PCI_DEVFN_SATA _PCI_DEVFN(SATA, 0) #define PCI_DEV_SATA _PCI_DEV(SATA, 0) -#define PCI_DEV_SLOT_ESE 0x18 -#define PCI_DEVFN_ESE1 _PCI_DEVFN(ESE, 0) -#define PCI_DEVFN_ESE2 _PCI_DEVFN(ESE, 1) -#define PCI_DEVFN_ESE3 _PCI_DEVFN(ESE, 2) -#define PCI_DEV_ESE1 _PCI_DEV(ESE, 0) -#define PCI_DEV_ESE2 _PCI_DEV(ESE, 1) -#define PCI_DEV_ESE3 _PCI_DEV(ESE, 2) +#define PCI_DEV_SLOT_ISSE 0x18 +#define PCI_DEVFN_ISSE1 _PCI_DEVFN(ESE, 0) +#define PCI_DEVFN_ISSE2 _PCI_DEVFN(ESE, 1) +#define PCI_DEVFN_ISSE3 _PCI_DEVFN(ESE, 2) +#define PCI_DEV_ISSE1 _PCI_DEV(ESE, 0) +#define PCI_DEV_ISSE2 _PCI_DEV(ESE, 1) +#define PCI_DEV_ISSE3 _PCI_DEV(ESE, 2) #define PCI_DEV_SLOT_SIO1 0x19 #define PCI_DEVFN_I2C4 _PCI_DEVFN(SIO1, 0) |